1789 		bus_write_1(bar->b_res, REG_SPR, REG_ACR);  in puc_config_advantech()
1790 		bus_write_1(bar->b_res, REG_ICR, acr);  in puc_config_advantech()
1902 		bus_write_1(bar->b_res, REG_LCR, LCR_DLAB);  in puc_config_quatech()
1903 		bus_write_1(bar->b_res, REG_SPR, 0);  in puc_config_quatech()
1905 		bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock);  in puc_config_quatech()
1907 		bus_write_1(bar->b_res, REG_LCR, 0);  in puc_config_quatech()
1994 		bus_write_1(bar->b_res, 0x250, 0x89);  in puc_config_syba()
1995 		bus_write_1(bar->b_res, 0x3f0, 0x87);  in puc_config_syba()
1996 		bus_write_1(bar->b_res, 0x3f0, 0x87);  in puc_config_syba()
2000 			bus_write_1(bar->b_res, efir, 0x09);  in puc_config_syba()
2004 			bus_write_1(bar->b_res, efir, 0x16);  in puc_config_syba()
2006 			bus_write_1(bar->b_res, efir, 0x16);  in puc_config_syba()
2007 			bus_write_1(bar->b_res, efir + 1, v | 0x04);  in puc_config_syba()
2008 			bus_write_1(bar->b_res, efir, 0x16);  in puc_config_syba()
2009 			bus_write_1(bar->b_res, efir + 1, v & ~0x04);  in puc_config_syba()
2011 			bus_write_1(bar->b_res, efir, 0x23);  in puc_config_syba()
2012 			bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);  in puc_config_syba()
2013 			bus_write_1(bar->b_res, efir, 0x24);  in puc_config_syba()
2014 			bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);  in puc_config_syba()
2015 			bus_write_1(bar->b_res, efir, 0x25);  in puc_config_syba()
2016 			bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);  in puc_config_syba()
2017 			bus_write_1(bar->b_res, efir, 0x17);  in puc_config_syba()
2018 			bus_write_1(bar->b_res, efir + 1, 0x03);  in puc_config_syba()
2019 			bus_write_1(bar->b_res, efir, 0x28);  in puc_config_syba()
2020 			bus_write_1(bar->b_res, efir + 1, 0x43);  in puc_config_syba()
2023 		bus_write_1(bar->b_res, 0x250, 0xaa);  in puc_config_syba()
2024 		bus_write_1(bar->b_res, 0x3f0, 0xaa);  in puc_config_syba()
2203 			bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,  in puc_config_oxford_pcie()