| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsLegalizerInfo.cpp | 381 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); in legalizeCustom()
410 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); in legalizeCustom()
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| H A D | MipsCallLowering.cpp | 240 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 74 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
520 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0), in saveVarArgRegisters()
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| H A D | RISCVLegalizerInfo.cpp | 769 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, IndexReg); in legalizeBRJT()
786 TargetReg = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, Load).getReg(0); in legalizeBRJT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 85 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 277 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
648 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0), in saveVarArgRegisters()
678 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0), in saveVarArgRegisters()
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| H A D | AArch64PostLegalizerCombiner.cpp | 335 auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg, in applySplitStoreZero128()
722 auto NewPtr = MIB.buildPtrAdd(MRI.getType(SInfo.St->getPointerReg()), in tryOptimizeConsecStores()
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| H A D | AArch64PreLegalizerCombiner.cpp | 226 B.buildPtrAdd( in applyFoldGlobalOffset()
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| H A D | AArch64LegalizerInfo.cpp | 1986 auto ListTmp = MIRBuilder.buildPtrAdd(PtrTy, List, AlignMinus1.getReg(0)); in legalizeVaArg()
2000 auto NewList = MIRBuilder.buildPtrAdd(PtrTy, DstPtr, Size.getReg(0)); in legalizeVaArg()
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| H A D | AArch64PostLegalizerLowering.cpp | 462 Builder.buildPtrAdd(MRI.getType(StackTemp.getReg(0)), StackTemp, Mul) in applyNonConstInsert()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 102 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 202 MachineIRBuilder::buildPtrAdd(const DstOp &Res, const SrcOp &Op0, in buildPtrAdd() function in MachineIRBuilder
224 return buildPtrAdd(Res, Op0, Cst.getReg(0)); in materializePtrAdd()
466 auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset); in buildLoadFromOffset()
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| H A D | LegalizerHelper.cpp | 4173 auto SmallPtr = MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); in lowerLoad()
4281 MIRBuilder.buildPtrAdd(PtrTy, PtrReg, OffsetCst); in lowerStore()
4862 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); in getVectorElementPointer()
9587 auto AddDst = MIRBuilder.buildPtrAdd(PtrTy, VAList, AlignAmt); in lowerVAArg()
9600 auto Succ = MIRBuilder.buildPtrAdd(PtrTy, VAList, IncAmt); in lowerVAArg()
9825 Ptr = MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); in lowerMemset()
9965 LoadPtr = MIB.buildPtrAdd(SrcTy, Src, Offset).getReg(0); in lowerMemcpy()
9973 StorePtr = MIB.buildPtrAdd(DstTy, Dst, Offset).getReg(0); in lowerMemcpy()
10063 LoadPtr = MIB.buildPtrAdd(SrcTy, Src, Offset).getReg(0); in lowerMemmove()
10081 StorePtr = MIB.buildPtrAdd(DstTy, Dst, Offset).getReg(0); in lowerMemmove()
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| H A D | IRTranslator.cpp | 1647 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0)) in translateGetElementPtr()
1676 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0); in translateGetElementPtr()
1687 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0), in translateGetElementPtr()
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| H A D | CombinerHelper.cpp | 2574 auto PtrAdd = Builder.buildPtrAdd(PtrTy, LHS, RHS); in applyCombineAddP2IToPtrAdd()
4878 Builder.buildPtrAdd(PtrTy, Src1Reg, RHS->getOperand(1).getReg()); in matchReassocConstantInnerRHS()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 113 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 227 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
403 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
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| H A D | AMDGPURegBankLegalizeHelper.cpp | 79 BasePlusOffset = B.buildPtrAdd({PtrRB, PtrTy}, Base, Offset).getReg(0); in splitLoad()
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| H A D | AMDGPULegalizerInfo.cpp | 2298 B.buildPtrAdd(LoadAddr, KernargPtrReg, in getSegmentAperture()
2320 B.buildPtrAdd(LoadAddr, QueuePtr, in getSegmentAperture()
4484 return B.buildPtrAdd(PtrTy, KernArgReg, COffset).getReg(0); in getKernargParameterPtr()
5660 B.buildPtrAdd(DstReg, KernargPtrReg, B.buildConstant(IdxTy, Offset).getReg(0)); in getImplicitArgPtr()
7002 B.buildPtrAdd(LoadAddr, KernargPtrReg, in legalizeTrapHsaQueuePtr()
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| H A D | AMDGPURegisterBankInfo.cpp | 1213 auto Tmp1 = B.buildPtrAdd(PtrTy, OldSP, in applyMappingDynStackAlloc()
1220 auto PtrAdd = B.buildPtrAdd(PtrTy, Dst, ScaledSize); in applyMappingDynStackAlloc()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 517 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
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