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Searched refs:buildMul (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUAtomicOptimizer.cpp639 static Value *buildMul(IRBuilder<> &B, Value *LHS, Value *RHS) { in buildMul() function
777 NewV = buildMul(B, V, Ctpop); in optimizeAtomic()
806 NewV = buildMul(B, V, B.CreateAnd(Ctpop, 1)); in optimizeAtomic()
922 LaneOffset = buildMul(B, V, Mbcnt); in optimizeAtomic()
935 LaneOffset = buildMul(B, V, B.CreateAnd(Mbcnt, 1)); in optimizeAtomic()
H A DAMDGPULegalizerInfo.cpp4030 auto Mul = B.buildMul(S32, Src0[j0], Src1[j1]); in buildMultiply()
4546 auto NegYZ = B.buildMul(S32, NegY, Z); in legalizeUnsignedDIV_REM32Impl()
4551 auto R = B.buildSub(S32, X, B.buildMul(S32, Q, Y)); in legalizeUnsignedDIV_REM32Impl()
4631 auto MulLo1 = B.buildMul(S64, NegDenom, Rcp); in legalizeUnsignedDIV_REM64Impl()
4642 auto MulLo2 = B.buildMul(S64, NegDenom, Add1); in legalizeUnsignedDIV_REM64Impl()
4658 auto Mul3 = B.buildMul(S64, Denom, MulHi3); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPURegisterBankInfo.cpp1612 Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0); in applyMappingMAD_64_32()
2194 Register MulLoHi = B.buildMul(HalfTy, Src0Regs[0], Src1Regs[1]).getReg(0); in applyMappingSMULU64()
2196 Register MulHiLo = B.buildMul(HalfTy, Src0Regs[1], Src1Regs[0]).getReg(0); in applyMappingSMULU64()
2198 B.buildMul(DefRegs[0], Src0Regs[0], Src1Regs[0]); in applyMappingSMULU64()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp872 MIB.buildMul(Dst, VLENB, MIB.buildConstant(XLenTy, Val / 8)); in legalizeVScale()
876 MIB.buildMul(Dst, VScale, MIB.buildConstant(XLenTy, Val)); in legalizeVScale()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DIRTranslator.cpp1672 MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0); in translateGetElementPtr()
3111 MIRBuilder.buildMul(AllocSize, NumElts, TySize); in translateAlloca()
3224 auto ScaledIndex = MIRBuilder.buildMul( in translateInsertVector()
3302 auto ScaledIndex = MIRBuilder.buildMul( in translateExtractVector()
H A DLegalizerHelper.cpp2053 MIRBuilder.buildMul(Dst, ZExt, C); in narrowScalar()
3676 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); in bitcastExtractVectorElt()
4443 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); in lower()
4858 auto Mul = MIRBuilder.buildMul(IdxTy, Index, in getVectorElementPointer()
6512 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); in multiplyRegisters()
6523 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); in multiplyRegisters()
7243 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); in lowerBitCount()
9229 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); in lowerSMULH_UMULH()
9714 Val = MIB.buildMul(ExtType, ZExt, MagicMI).getReg(0); in getMemsetValue()
H A DCombinerHelper.cpp5365 return MIB.buildMul(Ty, Res, Factor); in buildUDivorURemUsingMul()
5465 auto Prod = MIB.buildMul(Ty, ret, RHS); in buildUDivorURemUsingMul()
5636 return MIB.buildMul(Ty, Res, Factor); in buildSDivUsingMul()
5698 Factor = MIB.buildMul(Ty, LHS, Factor).getReg(0); in buildSDivUsingMul()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp460 Register Mul = Builder.buildMul(IdxTy, And, EltSize).getReg(0); in applyNonConstInsert()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1847 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,