| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUAtomicOptimizer.cpp | 657 static Value *buildMul(IRBuilder<> &B, Value *LHS, Value *RHS) { in buildMul() function
796 NewV = buildMul(B, V, Ctpop); in optimizeAtomic()
825 NewV = buildMul(B, V, B.CreateAnd(Ctpop, 1)); in optimizeAtomic()
935 LaneOffset = buildMul(B, V, Mbcnt); in optimizeAtomic()
948 LaneOffset = buildMul(B, V, B.CreateAnd(Mbcnt, 1)); in optimizeAtomic()
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| H A D | AMDGPULegalizerInfo.cpp | 3972 auto Mul = B.buildMul(S32, Src0[j0], Src1[j1]); in buildMultiply()
4488 auto NegYZ = B.buildMul(S32, NegY, Z); in legalizeUnsignedDIV_REM32Impl()
4493 auto R = B.buildSub(S32, X, B.buildMul(S32, Q, Y)); in legalizeUnsignedDIV_REM32Impl()
4573 auto MulLo1 = B.buildMul(S64, NegDenom, Rcp); in legalizeUnsignedDIV_REM64Impl()
4584 auto MulLo2 = B.buildMul(S64, NegDenom, Add1); in legalizeUnsignedDIV_REM64Impl()
4600 auto Mul3 = B.buildMul(S64, Denom, MulHi3); in legalizeUnsignedDIV_REM64Impl()
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| H A D | AMDGPURegisterBankInfo.cpp | 1584 Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0); in applyMappingMAD_64_32()
2166 Register MulLoHi = B.buildMul(HalfTy, Src0Regs[0], Src1Regs[1]).getReg(0); in applyMappingSMULU64()
2168 Register MulHiLo = B.buildMul(HalfTy, Src0Regs[1], Src1Regs[0]).getReg(0); in applyMappingSMULU64()
2170 B.buildMul(DefRegs[0], Src0Regs[0], Src1Regs[0]); in applyMappingSMULU64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVLegalizerInfo.cpp | 617 MIB.buildMul(Dst, VLENB, MIB.buildConstant(XLenTy, Val / 8)); in legalizeVScale()
621 MIB.buildMul(Dst, VScale, MIB.buildConstant(XLenTy, Val)); in legalizeVScale()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1753 MIRBuilder.buildMul(Dst, ZExt, C); in narrowScalar()
3264 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); in bitcastExtractVectorElt()
3805 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); in lower()
4181 auto Mul = MIRBuilder.buildMul(IdxTy, Index, in getVectorElementPointer()
5819 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); in multiplyRegisters()
5830 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); in multiplyRegisters()
6553 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); in lowerBitCount()
8283 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); in lowerSMULH_UMULH()
8752 Val = MIB.buildMul(ExtType, ZExt, MagicMI).getReg(0); in getMemsetValue()
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| H A D | IRTranslator.cpp | 1660 MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0); in translateGetElementPtr()
3064 MIRBuilder.buildMul(AllocSize, NumElts, TySize); in translateAlloca()
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| H A D | CombinerHelper.cpp | 5231 return MIB.buildMul(Ty, Res, Factor); in buildUDivUsingMul()
5476 return MIB.buildMul(Ty, Res, Factor); in buildSDivUsingMul()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 442 Register Mul = Builder.buildMul(IdxTy, And, EltSize).getReg(0); in applyNonConstInsert()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 1706 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
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