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Searched refs:buildInstr (Results 1 – 25 of 50) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h418 MachineInstrBuilder buildInstr(unsigned Opcode) { in buildInstr() function
545 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1}); in buildPtrMask()
606 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1}); in buildUAddo()
612 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1}); in buildUSubo()
618 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1}); in buildSAddo()
624 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1}); in buildSSubo()
644 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, in buildUAdde()
652 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, in buildUSube()
660 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, in buildSAdde()
668 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, in buildSSube()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp131 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); in buildDbgLabel()
140 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC); in buildDynStackAlloc()
150 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX); in buildFrameIndex()
163 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE); in buildGlobalValue()
172 auto MIB = buildInstr(TargetOpcode::G_CONSTANT_POOL); in buildConstantPool()
180 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {}) in buildJumpTable()
208 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}, Flags); in buildPtrAdd()
293 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); in buildBr()
298 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
306 return buildInstr(TargetOpcode::G_BRJT) in buildBrJT()
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H A DCombinerHelperCasts.cpp165 B.buildInstr(Ext->getOpcode(), {Dst}, {Src}); in matchTruncateOfExt()
224 auto True = B.buildInstr(Cast->getOpcode(), {DstTy}, {TrueReg}); in matchCastOfSelect()
225 auto False = B.buildInstr(Cast->getOpcode(), {DstTy}, {FalseReg}); in matchCastOfSelect()
258 B.buildInstr(Second->getOpcode(), {Dst}, {Src}); in matchExtOfExt()
326 B.buildInstr(Cast->getOpcode(), {ElemTy}, {BV->getSourceReg(I)}); in matchCastOfBuildVector()
355 B.buildInstr(BinOp->getOpcode(), {Dst}, {LHS, RHS}); in matchNarrowBinop()
H A DCSEMIRBuilder.cpp179 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() function in CSEMIRBuilder
309 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
313 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
330 MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
H A DIRTranslator.cpp326 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
342 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags); in translateUnaryOp()
1582 MIRBuilder.buildInstr(Opcode, {Res}, {Op}, Flags); in translateCast()
1722 auto ICall = MIRBuilder.buildInstr(Opcode); in translateMemFunc()
1791 MIRBuilder.buildInstr(Opcode, {}, ArrayRef<llvm::SrcOp>{Code}); in translateTrap()
1793 MIRBuilder.buildInstr(Opcode); in translateTrap()
1849 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {}); in getStackGuard()
1869 MIRBuilder.buildInstr( in translateOverflowIntrinsic()
1882 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale }); in translateFixedPointIntrinsic()
2040 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
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H A DLegalizerHelper.cpp1592 MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, {Unmerge.getReg(i)}) in narrowScalar()
1766 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); in narrowScalar()
1983 .buildInstr( in narrowScalar()
2009 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, in narrowScalar()
2085 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); in widenScalarSrc()
2101 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); in widenScalarDst()
2110 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); in narrowScalarDst()
2357 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); in widenScalarUnmergeValues()
2537 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); in widenScalarAddSubOverflow()
2538 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); in widenScalarAddSubOverflow()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp329 .buildInstr(NegOpc, {ShAmtReg}, {Register(RISCV::X0), Reg}); in selectShiftMask()
339 .buildInstr(RISCV::XORI, {ShAmtReg}, {Reg}) in selectShiftMask()
431 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
443 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
482 .buildInstr(RISCV::SRLIW, {DstReg}, {RegY}) in selectSHXADDOp()
519 .buildInstr(RISCV::SLLI, {DstReg}, {RegX}) in selectSHXADD_UWOp()
752 auto FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg}); in select()
766 MachineInstrBuilder PairF64 = MIB.buildInstr( in select()
792 auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(CC), {}, {LHS, RHS}) in select()
839 MachineInstr *ExtractLo = MIB.buildInstr(RISCV::FMV_X_W_FPR64, {Lo}, {Src}); in selectUnmergeValues()
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H A DRISCVLegalizerInfo.cpp860 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
863 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
866 MIB.buildInstr(RISCV::G_READ_VLENB, {Dst}, {}); in legalizeVScale()
871 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
874 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
964 return MIB.buildInstr(RISCV::G_VMSET_VL, {MaskTy}, {VL}); in buildAllOnesMask()
991 return MIB.buildInstr(RISCV::G_SPLAT_VECTOR_SPLIT_I64_VL, {Dst}, in buildSplatPartsS64WithVL()
1035 MIB.buildInstr(RISCV::G_VMSET_VL, {Dst}, {VL}); in legalizeSplatVector()
1041 MIB.buildInstr(RISCV::G_VMCLR_VL, {Dst}, {VL}); in legalizeSplatVector()
1147 auto Slidedown = MIB.buildInstr( in legalizeExtractSubvector()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.cpp146 return MIRBuilder.buildInstr(SPIRV::OpTypeBool) in getOpTypeBool()
178 MIRBuilder.buildInstr(SPIRV::OpExtension) in getOpTypeInt()
180 MIRBuilder.buildInstr(SPIRV::OpCapability) in getOpTypeInt()
185 MIRBuilder.buildInstr(SPIRV::OpExtension) in getOpTypeInt()
187 MIRBuilder.buildInstr(SPIRV::OpCapability) in getOpTypeInt()
190 return MIRBuilder.buildInstr(SPIRV::OpTypeInt) in getOpTypeInt()
200 return MIRBuilder.buildInstr(SPIRV::OpTypeFloat) in getOpTypeFloat()
208 return MIRBuilder.buildInstr(SPIRV::OpTypeVoid) in getOpTypeVoid()
276 return MIRBuilder.buildInstr(SPIRV::OpTypeVector) in getOpTypeVector()
313 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull) in createConstFP()
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H A DSPIRVBuiltins.cpp634 auto MIB = MIRBuilder.buildInstr(Opcode);
653 MIRBuilder.buildInstr(SPIRV::OpStore) in buildAtomicInitInst()
686 MIRBuilder.buildInstr(SPIRV::OpAtomicLoad) in buildAtomicLoadInst()
709 MIRBuilder.buildInstr(SPIRV::OpAtomicStore) in buildAtomicStoreInst()
803 MIRBuilder.buildInstr(Opcode) in buildAtomicCompareExchangeInst()
813 MIRBuilder.buildInstr(SPIRV::OpStore).addUse(ExpectedArg).addUse(Tmp); in buildAtomicCompareExchangeInst()
857 MIRBuilder.buildInstr(TargetOpcode::G_FNEG) in buildAtomicRMWInst()
865 MIRBuilder.buildInstr(Opcode) in buildAtomicRMWInst()
886 MIRBuilder.buildInstr(Opcode) in buildAtomicFloatingRMWInst()
925 auto MIB = MIRBuilder.buildInstr(Opcode); in buildAtomicFlagInst()
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H A DSPIRVCallLowering.cpp58 return MIRBuilder.buildInstr(SPIRV::OpReturnValue) in lowerReturn()
63 MIRBuilder.buildInstr(SPIRV::OpReturn); in lowerReturn()
442 MachineInstrBuilder MB = MIRBuilder.buildInstr(SPIRV::OpFunction) in lowerFormalArguments()
459 auto MIB = MIRBuilder.buildInstr(SPIRV::OpFunctionParameter) in lowerFormalArguments()
478 auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint) in lowerFormalArguments()
716 auto MIB = MIRBuilder.buildInstr(CallOp) in lowerCall()
H A DSPIRVUtils.cpp116 auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target); in buildOpName()
143 auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate) in buildOpDecorate()
163 auto MIB = MIRBuilder.buildInstr(SPIRV::OpMemberDecorate) in buildOpMemberDecorate()
196 auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate) in buildOpSpirvDecorations()
876 MIRBuilder.buildInstr(Opcode).addDef(ReturnRegister).addUse(TypeID); in createContinuedInstructions()
885 auto MIB = MIRBuilder.buildInstr(ContinuedOpcode); in createContinuedInstructions()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp721 MIB.buildInstr(TargetOpcode::REG_SEQUENCE, {DesiredClass}, {}); in createTuple()
938 MIB.buildInstr(TargetOpcode::COPY, {To}, {}).addReg(SrcReg, 0, SubReg); in copySubReg()
1198 auto FCSel = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1347 auto SelectInst = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1623 MIB.buildInstr(Opc).addReg(TestReg).addImm(Bit).addMBB(DstMBB); in emitTestBit()
1685 auto BranchMI = MIB.buildInstr(Opc, {}, {CompareReg}).addMBB(DestMBB); in emitCBZ()
1702 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB); in selectCompareBranchFedByFCmp()
1704 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB); in selectCompareBranchFedByFCmp()
1817 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB); in selectCompareBranchFedByICmp()
1846 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
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H A DAArch64PreLegalizerCombiner.cpp332 auto Dot = Builder.buildInstr(DotOpcode, {MidTy}, in applyExtAddvToUdotAddv()
396 .buildInstr(DotOpcode, {MRI.getType(Zeroes)}, in applyExtAddvToUdotAddv()
501 B.buildInstr(std::get<1>(MatchInfo) ? TargetOpcode::G_SEXT in applyExtUaddvToUaddlv()
512 B.buildInstr(Opc, {addlvTy}, {WorkingRegisters[I]}).getReg(0); in applyExtUaddvToUaddlv()
520 WorkingRegisters[I] = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, in applyExtUaddvToUaddlv()
524 Register extractReg = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, in applyExtUaddvToUaddlv()
546 B.buildInstr(std::get<1>(MatchInfo) ? TargetOpcode::G_SEXT in applyExtUaddvToUaddlv()
591 Register Ext1Reg = B.buildInstr(Opc, {MidTy}, {SrcReg1}).getReg(0); in applyPushAddSubExt()
592 Register Ext2Reg = B.buildInstr(Opc, {MidTy}, {SrcReg2}).getReg(0); in applyPushAddSubExt()
594 B.buildInstr(MI.getOpcode(), {MidTy}, {Ext1Reg, Ext2Reg}).getReg(0); in applyPushAddSubExt()
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H A DAArch64PostLegalizerLowering.cpp386 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
401 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, in applyEXT()
415 auto Rev = MIRBuilder.buildInstr(AArch64::G_REV64, {DstTy}, {Src}); in applyFullRev()
416 MIRBuilder.buildInstr(AArch64::G_EXT, {Dst}, {Rev, Rev, Cst}); in applyFullRev()
560 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef}); in applyVAshrLshrImm()
781 B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane}); in applyDupLane()
823 B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()}, in applyBuildVectorToDup()
945 auto FCmp = MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}); in getVectorFCMP()
950 return MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}).getReg(0); in getVectorFCMP()
954 return MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {LHS, RHS}).getReg(0); in getVectorFCMP()
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H A DAArch64LegalizerInfo.cpp1524 MIRBuilder.buildInstr(TargetOpcode::G_FSHR, {MI.getOperand(0).getReg()}, in legalizeFunnelShift()
1603 auto ADRP = MIRBuilder.buildInstr(AArch64::ADRP, {LLT::pointer(0, 64)}, {}) in legalizeSmallCMGlobalValue()
1624 ADRP = MIRBuilder.buildInstr(AArch64::MOVKXi, {LLT::pointer(0, 64)}, {ADRP}) in legalizeSmallCMGlobalValue()
1631 MIRBuilder.buildInstr(AArch64::G_ADD_LOW, {DstReg}, {ADRP}) in legalizeSmallCMGlobalValue()
1644 MIB.buildInstr(Opcode, {MI.getOperand(0)}, in legalizeIntrinsic()
1700 MIB.buildInstr(AArch64::G_AARCH64_PREFETCH).addImm(PrfOp).add(AddrVal); in legalizeIntrinsic()
1737 MIB.buildInstr(Opc, {MI.getOperand(0)}, {MI.getOperand(2)}); in legalizeIntrinsic()
1761 MIB.buildInstr(Opc, {MidTy}, {SrcReg})->getOperand(0).getReg(); in legalizeIntrinsic()
1764 Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy}, in legalizeIntrinsic()
1799 MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)}); in legalizeIntrinsic()
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H A DAArch64PostLegalizerCombiner.cpp121 B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1}); in applyExtractVecEltPairwiseAdd()
231 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS}); in matchAArch64MulConstCombine()
380 B.buildInstr( in applyOrToBSP()
432 B.buildInstr(TargetOpcode::G_BITCAST, {HalfTy}, {SrcReg}).getReg(0); in applyCombineMulCMLT()
437 B.buildInstr(TargetOpcode::G_BITCAST, {DstReg}, {CMLTReg}).getReg(0); in applyCombineMulCMLT()
552 B.buildInstr(IsZExt ? AArch64::G_UMULL : AArch64::G_SMULL, in applyExtMulToMULL()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUGlobalISelDivergenceLowering.cpp176 B.buildInstr(AndN2Op, {PrevMaskedReg}, {PrevRegCopy, ExecReg}); in buildMergeLaneMasks()
177 B.buildInstr(AndOp, {CurMaskedReg}, {ExecReg, CurRegCopy}); in buildMergeLaneMasks()
178 B.buildInstr(OrOp, {DstReg}, {PrevMaskedReg, CurMaskedReg}); in buildMergeLaneMasks()
220 B.buildInstr(AMDGPU::COPY, {VgprReg}, {Reg}) in lowerTemporalDivergence()
264 auto ImplDef = B.buildInstr(AMDGPU::IMPLICIT_DEF, {BoolS1}, {}); in lowerTemporalDivergenceI1()
H A DAMDGPURegBankLegalizeHelper.cpp201 Lo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val0, Amt0}).getReg(0); in lowerUnpackBitShift()
202 Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0); in lowerUnpackBitShift()
208 Lo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val0, Amt0}).getReg(0); in lowerUnpackBitShift()
209 Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0); in lowerUnpackBitShift()
248 auto SHRSrc = B.buildInstr(SHROpc, {{VgprRB, S64}}, {Src, LSBit}); in lowerV_BFE()
258 B.buildInstr(SHROpc, {Dst}, {SignBit, Amt}); in lowerV_BFE()
272 auto Lo = B.buildInstr(BFXOpc, {VgprRB_S32}, {SHRSrcLo, Zero, Width}); in lowerV_BFE()
285 auto Hi = B.buildInstr(BFXOpc, {VgprRB_S32}, {SHRSrcHi, Zero, Amt}); in lowerV_BFE()
315 auto S_BFE = B.buildInstr(Opc, {{SgprRB, Ty}}, in lowerS_BFE()
335 B.buildInstr(Opc, {{VgprRB, Ty}}, {Op1.getReg(0), Op2.getReg(0)}, Flags); in lowerSplitTo32()
[all …]
H A DAMDGPUGlobalISelUtils.cpp139 return B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {{SgprRB, Ty}}, {VgprSrc}) in buildReadAnyLane()
153 B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {SgprDst}, {VgprSrc}); in buildReadAnyLane()
H A DAMDGPUPostLegalizerCombiner.cpp202 B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags()); in applySelectFCmpToFMinFMaxLegacy()
239 B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, {SrcReg}, in applyUCharToFloat()
242 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, {SrcReg}, in applyUCharToFloat()
358 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) in materialize32BitImm()
599 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
612 MachineInstrBuilder PairF64 = B.buildInstr( in select()
801 MachineInstrBuilder MIB = B.buildInstr( in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/GISel/
H A DBPFCallLowering.cpp31 MIRBuilder.buildInstr(BPF::RET); in lowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp334 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); in lowerCall()
376 MIRBuilder.buildInstr(X86::MOV8ri) in lowerCall()
422 MIRBuilder.buildInstr(AdjStackUp) in lowerCall()

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