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Searched refs:buildInstr (Results 1 – 25 of 42) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h406 MachineInstrBuilder buildInstr(unsigned Opcode) { in buildInstr() function
533 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1}); in buildPtrMask()
594 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1}); in buildUAddo()
600 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1}); in buildUSubo()
606 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1}); in buildSAddo()
612 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1}); in buildSSubo()
632 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, in buildUAdde()
640 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, in buildUSube()
648 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, in buildSAdde()
656 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, in buildSSube()
[all …]
H A DCSEMIRBuilder.h95 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp131 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); in buildDbgLabel()
140 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC); in buildDynStackAlloc()
150 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX); in buildFrameIndex()
163 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE); in buildGlobalValue()
172 auto MIB = buildInstr(TargetOpcode::G_CONSTANT_POOL); in buildConstantPool()
180 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {}) in buildJumpTable()
208 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}, Flags); in buildPtrAdd()
293 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); in buildBr()
298 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
306 return buildInstr(TargetOpcode::G_BRJT) in buildBrJT()
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H A DCSEMIRBuilder.cpp175 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() function in CSEMIRBuilder
303 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
307 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
324 MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
H A DIRTranslator.cpp315 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
328 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags); in translateUnaryOp()
1570 MIRBuilder.buildInstr(Opcode, {Res}, {Op}, Flags); in translateCast()
1710 auto ICall = MIRBuilder.buildInstr(Opcode); in translateMemFunc()
1783 MIRBuilder.buildInstr(Opcode, {}, ArrayRef<llvm::SrcOp>{Code}); in translateTrap()
1785 MIRBuilder.buildInstr(Opcode); in translateTrap()
1841 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {}); in getStackGuard()
1861 MIRBuilder.buildInstr( in translateOverflowIntrinsic()
1874 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale }); in translateFixedPointIntrinsic()
2026 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
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H A DLegalizerHelper.cpp1329 MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, {Unmerge.getReg(i)}) in narrowScalar()
1503 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); in narrowScalar()
1685 .buildInstr( in narrowScalar()
1711 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, in narrowScalar()
1785 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); in widenScalarSrc()
1801 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); in widenScalarDst()
1810 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); in narrowScalarDst()
2059 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); in widenScalarUnmergeValues()
2239 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); in widenScalarAddSubOverflow()
2240 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); in widenScalarAddSubOverflow()
[all …]
H A DCombinerHelper.cpp1458 auto MIB = Builder.buildInstr(NewOpcode); in applyCombineIndexedLoadStore()
1564 Builder.buildInstr(IsSigned ? TargetOpcode::G_SDIVREM in applyCombineDivRem()
1949 Builder.buildInstr(Opcode, {DestType}, {Shift1Base, Const}).getReg(0); in applyShiftOfShiftedLogic()
1960 .buildInstr(Opcode, {DestType}, in applyShiftOfShiftedLogic()
1965 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()
2003 B.buildInstr(SrcDef->getOpcode(), {DstReg}, {S1, S2}); in matchCommuteShift()
2580 Builder.buildInstr(SrcExtOp, {DstReg}, {Reg}); in applyCombineExtOfExt()
2613 Builder.buildInstr(SrcExtOp, {DstReg}, {SrcReg}); in applyCombineTruncOfExt()
2711 .buildInstr(ShiftMI->getOpcode(), {NewShiftTy}, {ShiftSrc, ShiftAmt}) in applyCombineTruncOfShift()
2945 Builder.buildInstr( in applyFunnelShiftConstantModulo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp222 .buildInstr(NegOpc, {ShAmtReg}, {Register(RISCV::X0), Reg}); in selectShiftMask()
232 .buildInstr(RISCV::XORI, {ShAmtReg}, {Reg}) in selectShiftMask()
281 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
293 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
332 .buildInstr(RISCV::SRLIW, {DstReg}, {RegY}) in selectSHXADDOp()
371 .buildInstr(RISCV::SLLI, {DstReg}, {RegX}) in selectSHXADD_UWOp()
588 auto FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg}); in select()
602 MachineInstrBuilder PairF64 = MIB.buildInstr( in select()
629 auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(CC), {}, {LHS, RHS}) in select()
647 MIB.buildInstr(RISCV::SLLI, {&RISCV::GPRRegClass}, {MI.getOperand(2)}) in select()
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H A DRISCVLegalizerInfo.cpp605 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
608 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
611 MIB.buildInstr(RISCV::G_READ_VLENB, {Dst}, {}); in legalizeVScale()
616 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
619 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
669 return MIB.buildInstr(RISCV::G_VMSET_VL, {MaskTy}, {VL}); in buildAllOnesMask()
696 return MIB.buildInstr(RISCV::G_SPLAT_VECTOR_SPLIT_I64_VL, {Dst}, in buildSplatPartsS64WithVL()
740 MIB.buildInstr(RISCV::G_VMSET_VL, {Dst}, {VL}); in legalizeSplatVector()
746 MIB.buildInstr(RISCV::G_VMCLR_VL, {Dst}, {VL}); in legalizeSplatVector()
814 auto GFClass = MIB.buildInstr(RISCV::G_FCLASS, {sXLen}, {Src}); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.cpp89 return MIRBuilder.buildInstr(SPIRV::OpTypeBool) in getOpTypeBool()
119 MIRBuilder.buildInstr(SPIRV::OpExtension) in getOpTypeInt()
121 MIRBuilder.buildInstr(SPIRV::OpCapability) in getOpTypeInt()
124 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeInt) in getOpTypeInt()
133 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFloat) in getOpTypeFloat()
140 return MIRBuilder.buildInstr(SPIRV::OpTypeVoid) in getOpTypeVoid()
153 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeVector) in getOpTypeVector()
325 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI) in buildConstantInt()
330 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull) in buildConstantInt()
362 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantF) in buildConstantFP()
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H A DSPIRVBuiltins.cpp579 auto MIB = MIRBuilder.buildInstr(Opcode);
604 MIRBuilder.buildInstr(SPIRV::OpStore) in buildAtomicInitInst()
642 MIRBuilder.buildInstr(SPIRV::OpAtomicLoad) in buildAtomicLoadInst()
667 MIRBuilder.buildInstr(SPIRV::OpAtomicStore) in buildAtomicStoreInst()
767 MIRBuilder.buildInstr(Opcode) in buildAtomicCompareExchangeInst()
777 MIRBuilder.buildInstr(SPIRV::OpStore).addUse(ExpectedArg).addUse(Tmp); in buildAtomicCompareExchangeInst()
823 MIRBuilder.buildInstr(TargetOpcode::G_FNEG) in buildAtomicRMWInst()
831 MIRBuilder.buildInstr(Opcode) in buildAtomicRMWInst()
863 MIRBuilder.buildInstr(Opcode) in buildAtomicFloatingRMWInst()
902 auto MIB = MIRBuilder.buildInstr(Opcode); in buildAtomicFlagInst()
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H A DSPIRVCallLowering.cpp51 return MIRBuilder.buildInstr(SPIRV::OpReturnValue) in lowerReturn()
56 MIRBuilder.buildInstr(SPIRV::OpReturn); in lowerReturn()
395 MachineInstrBuilder MB = MIRBuilder.buildInstr(SPIRV::OpFunction) in lowerFormalArguments()
407 MIRBuilder.buildInstr(SPIRV::OpFunctionParameter) in lowerFormalArguments()
422 auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint) in lowerFormalArguments()
603 auto MIB = MIRBuilder.buildInstr(CallOp) in lowerCall()
H A DSPIRVUtils.cpp103 auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target); in buildOpName()
120 auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate) in buildOpDecorate()
149 auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate) in buildOpSpirvDecorations()
H A DSPIRVPreLegalizer.cpp394 MIB.buildInstr(SPIRV::ASSIGN_TYPE) in insertAssignInstr()
419 MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg()); in processInstr()
629 MIRBuilder.buildInstr(SPIRV::OpAsmTargetINTEL).addDef(AsmTargetReg); in insertInlineAsmProcess()
648 auto AsmMIB = MIRBuilder.buildInstr(SPIRV::OpAsmINTEL) in insertInlineAsmProcess()
665 MIRBuilder.buildInstr(SPIRV::OpDecorate) in insertInlineAsmProcess()
695 auto AsmCall = MIRBuilder.buildInstr(SPIRV::OpAsmCallINTEL) in insertInlineAsmProcess()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp714 MIB.buildInstr(TargetOpcode::REG_SEQUENCE, {DesiredClass}, {}); in createTuple()
931 MIB.buildInstr(TargetOpcode::COPY, {To}, {}).addReg(SrcReg, 0, SubReg); in copySubReg()
1190 auto FCSel = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1339 auto SelectInst = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1615 MIB.buildInstr(Opc).addReg(TestReg).addImm(Bit).addMBB(DstMBB); in emitTestBit()
1677 auto BranchMI = MIB.buildInstr(Opc, {}, {CompareReg}).addMBB(DestMBB); in emitCBZ()
1694 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB); in selectCompareBranchFedByFCmp()
1696 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB); in selectCompareBranchFedByFCmp()
1809 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB); in selectCompareBranchFedByICmp()
1838 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
[all …]
H A DAArch64PostLegalizerLowering.cpp384 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
399 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, in applyEXT()
542 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef}); in applyVAshrLshrImm()
763 B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane}); in applyDupLane()
807 B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()}, in applyBuildVectorToDup()
931 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}) in getVectorFCMP()
932 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}); in getVectorFCMP()
938 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
939 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}) in getVectorFCMP()
945 ? MIB.buildInstr(AArch64::G_FCMGEZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
[all …]
H A DAArch64PreLegalizerCombiner.cpp331 auto Dot = Builder.buildInstr(DotOpcode, {MidTy}, in applyExtAddvToUdotAddv()
395 .buildInstr(DotOpcode, {MRI.getType(Zeroes)}, in applyExtAddvToUdotAddv()
502 B.buildInstr(std::get<1>(MatchInfo) ? TargetOpcode::G_SEXT in applyExtUaddvToUaddlv()
513 B.buildInstr(Opc, {addlvTy}, {WorkingRegisters[I]}).getReg(0); in applyExtUaddvToUaddlv()
521 WorkingRegisters[I] = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, in applyExtUaddvToUaddlv()
525 Register extractReg = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, in applyExtUaddvToUaddlv()
547 B.buildInstr(std::get<1>(MatchInfo) ? TargetOpcode::G_SEXT in applyExtUaddvToUaddlv()
592 Register Ext1Reg = B.buildInstr(Opc, {MidTy}, {SrcReg1}).getReg(0); in applyPushAddSubExt()
593 Register Ext2Reg = B.buildInstr(Opc, {MidTy}, {SrcReg2}).getReg(0); in applyPushAddSubExt()
595 B.buildInstr(MI.getOpcode(), {MidTy}, {Ext1Reg, Ext2Reg}).getReg(0); in applyPushAddSubExt()
[all …]
H A DAArch64LegalizerInfo.cpp1397 MIRBuilder.buildInstr(TargetOpcode::G_FSHR, {MI.getOperand(0).getReg()}, in legalizeFunnelShift()
1476 auto ADRP = MIRBuilder.buildInstr(AArch64::ADRP, {LLT::pointer(0, 64)}, {}) in legalizeSmallCMGlobalValue()
1497 ADRP = MIRBuilder.buildInstr(AArch64::MOVKXi, {LLT::pointer(0, 64)}, {ADRP}) in legalizeSmallCMGlobalValue()
1504 MIRBuilder.buildInstr(AArch64::G_ADD_LOW, {DstReg}, {ADRP}) in legalizeSmallCMGlobalValue()
1567 MIB.buildInstr(AArch64::G_AARCH64_PREFETCH).addImm(PrfOp).add(AddrVal); in legalizeIntrinsic()
1608 MIB.buildInstr(Opc, {MI.getOperand(0)}, {MI.getOperand(2)}); in legalizeIntrinsic()
1635 MIB.buildInstr(Opc, {MidTy}, {SrcReg})->getOperand(0).getReg(); in legalizeIntrinsic()
1638 Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy}, in legalizeIntrinsic()
1669 MIB.buildInstr(TargetOpcode::G_FMAXIMUM, {MI.getOperand(0)}, in legalizeIntrinsic()
1672 MIB.buildInstr(TargetOpcode::G_FMINIMUM, {MI.getOperand(0)}, in legalizeIntrinsic()
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H A DAArch64PostLegalizerCombiner.cpp121 B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1}); in applyExtractVecEltPairwiseAdd()
231 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS}); in matchAArch64MulConstCombine()
380 B.buildInstr( in applyOrToBSP()
432 B.buildInstr(TargetOpcode::G_BITCAST, {HalfTy}, {SrcReg}).getReg(0); in applyCombineMulCMLT()
437 B.buildInstr(TargetOpcode::G_BITCAST, {DstReg}, {CMLTReg}).getReg(0); in applyCombineMulCMLT()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUGlobalISelDivergenceLowering.cpp175 B.buildInstr(AndN2Op, {PrevMaskedReg}, {PrevRegCopy, ExecReg}); in buildMergeLaneMasks()
176 B.buildInstr(AndOp, {CurMaskedReg}, {ExecReg, CurRegCopy}); in buildMergeLaneMasks()
177 B.buildInstr(OrOp, {DstReg}, {PrevMaskedReg, CurMaskedReg}); in buildMergeLaneMasks()
H A DAMDGPUPostLegalizerCombiner.cpp202 B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags()); in applySelectFCmpToFMinFMaxLegacy()
239 B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, {SrcReg}, in applyUCharToFloat()
242 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, {SrcReg}, in applyUCharToFloat()
358 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
H A DAMDGPUPreLegalizerCombiner.cpp191 B.buildInstr(AMDGPU::G_AMDGPU_CVT_PK_I16_I32, {V2S16}, in applyClampI64ToI16()
201 auto Med3 = B.buildInstr( in applyClampI64ToI16()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) in materialize32BitImm()
599 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
612 MachineInstrBuilder PairF64 = B.buildInstr( in select()
801 MachineInstrBuilder MIB = B.buildInstr( in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp335 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); in lowerCall()
377 MIRBuilder.buildInstr(X86::MOV8ri) in lowerCall()
423 MIRBuilder.buildInstr(AdjStackUp) in lowerCall()

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