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Searched refs:buildBuildVector (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp488 B.buildBuildVector(OrigRegs[0], Regs); in buildCopyFromRegs()
508 B.buildBuildVector(OrigRegs[0], EltMerges); in buildCopyFromRegs()
517 BuildVec = B.buildBuildVector(BVType, Regs).getReg(0); in buildCopyFromRegs()
546 BuildVec = B.buildBuildVector(BVType, BVRegs).getReg(0); in buildCopyFromRegs()
H A DCSEMIRBuilder.cpp304 return buildBuildVector(DstOps[0], ConstantRegs); in buildInstr()
H A DCombinerHelper.cpp389 Builder.buildBuildVector(NewDstReg, Ops); in applyCombineConcatVectors()
432 Builder.buildBuildVector(MI.getOperand(0).getReg(), Extracts); in applyCombineShuffleToBuildVector()
3127 Builder.buildBuildVector(MI.getOperand(0).getReg(), MatchInfo); in applyCombineInsertVecElts()
5353 Shift = MIB.buildBuildVector(ShiftAmtTy, Shifts).getReg(0); in buildUDivorURemUsingMul()
5354 Factor = MIB.buildBuildVector(Ty, Factors).getReg(0); in buildUDivorURemUsingMul()
5426 PreShift = MIB.buildBuildVector(ShiftAmtTy, PreShifts).getReg(0); in buildUDivorURemUsingMul()
5427 MagicFactor = MIB.buildBuildVector(Ty, MagicFactors).getReg(0); in buildUDivorURemUsingMul()
5428 NPQFactor = MIB.buildBuildVector(Ty, NPQFactors).getReg(0); in buildUDivorURemUsingMul()
5429 PostShift = MIB.buildBuildVector(ShiftAmtTy, PostShifts).getReg(0); in buildUDivorURemUsingMul()
5624 Shift = MIB.buildBuildVector(ShiftAmtTy, ExactShifts).getReg(0); in buildSDivUsingMul()
[all …]
H A DCombinerHelperCasts.cpp330 B.buildBuildVector(Dst, Casts); in matchCastOfBuildVector()
H A DLegalizerHelper.cpp179 MIRBuilder.buildBuildVector(DstReg, PartRegs); in insertParts()
1521 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
3685 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); in bitcastExtractVectorElt()
3874 MIRBuilder.buildBuildVector(CastTy, BitcastRegs).getReg(0); in bitcastConcatVector()
5710 Output = MIRBuilder.buildBuildVector(NarrowTy, SVOps).getReg(0); in fewerElementsVectorShuffle()
6452 MIRBuilder.buildBuildVector(DstReg, Elts); in equalizeVectorShuffleLengths()
6774 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalarExtract()
8551 MIRBuilder.buildBuildVector(DstReg, BuildVec); in lowerShuffleVector()
H A DMachineIRBuilder.cpp722 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res, in buildBuildVector() function in MachineIRBuilder
H A DIRTranslator.cpp3695 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
3712 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp651 return B.buildBuildVector(VectorTy, PointerParts).getReg(0); in castBufferRsrcToV4I32()
3266 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0); in legalizeAtomicCmpXChg()
5838 return B.buildBuildVector(LLT::fixed_vector(NumElts, S32), WideRegs) in handleD16VData()
5848 return B.buildBuildVector(LLT::fixed_vector(2, S32), PackedRegs) in handleD16VData()
5858 Reg = B.buildBuildVector(LLT::fixed_vector(6, S16), PackedRegs).getReg(0); in handleD16VData()
5869 return B.buildBuildVector(LLT::fixed_vector(4, S32), PackedRegs) in handleD16VData()
6370 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
6391 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
6395 B.buildBuildVector( in packImage16bitOpsToDwords()
6422 B.buildBuildVector(LLT::fixed_vector(NumAddrRegs, 32), AddrRegs); in convertImageAddrToPacked()
[all …]
H A DAMDGPURegisterBankInfo.cpp2123 B.buildBuildVector(MI.getOperand(0), Ops); in foldInsertEltToCmpSelect()
2125 auto Vec = B.buildBuildVector(MergeTy, Ops); in foldInsertEltToCmpSelect()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h698 return MIB.buildBuildVector(NewBVTy, NewSrcs).getReg(0); in findValueFromBuildVector()
H A DMachineIRBuilder.h1133 MachineInstrBuilder buildBuildVector(const DstOp &Res,