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Searched refs:buildBuildVector (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp489 B.buildBuildVector(OrigRegs[0], Regs); in buildCopyFromRegs()
509 B.buildBuildVector(OrigRegs[0], EltMerges); in buildCopyFromRegs()
518 BuildVec = B.buildBuildVector(BVType, Regs).getReg(0); in buildCopyFromRegs()
547 BuildVec = B.buildBuildVector(BVType, BVRegs).getReg(0); in buildCopyFromRegs()
H A DCSEMIRBuilder.cpp298 return buildBuildVector(DstOps[0], ConstantRegs); in buildInstr()
H A DCombinerHelper.cpp371 Builder.buildBuildVector(NewDstReg, Ops); in applyCombineConcatVectors()
3092 Builder.buildBuildVector(MI.getOperand(0).getReg(), MatchInfo); in applyCombineInsertVecElts()
5219 Shift = MIB.buildBuildVector(ShiftAmtTy, Shifts).getReg(0); in buildUDivUsingMul()
5220 Factor = MIB.buildBuildVector(Ty, Factors).getReg(0); in buildUDivUsingMul()
5292 PreShift = MIB.buildBuildVector(ShiftAmtTy, PreShifts).getReg(0); in buildUDivUsingMul()
5293 MagicFactor = MIB.buildBuildVector(Ty, MagicFactors).getReg(0); in buildUDivUsingMul()
5294 NPQFactor = MIB.buildBuildVector(Ty, NPQFactors).getReg(0); in buildUDivUsingMul()
5295 PostShift = MIB.buildBuildVector(ShiftAmtTy, PostShifts).getReg(0); in buildUDivUsingMul()
5464 Shift = MIB.buildBuildVector(ShiftAmtTy, Shifts).getReg(0); in buildSDivUsingMul()
5465 Factor = MIB.buildBuildVector(Ty, Factors).getReg(0); in buildSDivUsingMul()
H A DLegalizerHelper.cpp178 MIRBuilder.buildBuildVector(DstReg, PartRegs); in insertParts()
1258 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
3273 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); in bitcastExtractVectorElt()
3462 MIRBuilder.buildBuildVector(CastTy, BitcastRegs).getReg(0); in bitcastConcatVector()
5021 Output = MIRBuilder.buildBuildVector(NarrowTy, SVOps).getReg(0); in fewerElementsVectorShuffle()
5757 MIRBuilder.buildBuildVector(DstReg, Elts); in equalizeVectorShuffleLengths()
6082 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalarExtract()
7632 MIRBuilder.buildBuildVector(DstReg, BuildVec); in lowerShuffleVector()
H A DIRTranslator.cpp3529 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
3539 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
3556 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
H A DMachineIRBuilder.cpp710 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res, in buildBuildVector() function in MachineIRBuilder
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp638 return B.buildBuildVector(VectorTy, PointerParts).getReg(0); in castBufferRsrcToV4I32()
3208 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0); in legalizeAtomicCmpXChg()
5732 return B.buildBuildVector(LLT::fixed_vector(NumElts, S32), WideRegs) in handleD16VData()
5742 return B.buildBuildVector(LLT::fixed_vector(2, S32), PackedRegs) in handleD16VData()
5752 Reg = B.buildBuildVector(LLT::fixed_vector(6, S16), PackedRegs).getReg(0); in handleD16VData()
5763 return B.buildBuildVector(LLT::fixed_vector(4, S32), PackedRegs) in handleD16VData()
6240 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
6261 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
6265 B.buildBuildVector( in packImage16bitOpsToDwords()
6292 B.buildBuildVector(LLT::fixed_vector(NumAddrRegs, 32), AddrRegs); in convertImageAddrToPacked()
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H A DAMDGPURegisterBankInfo.cpp2095 B.buildBuildVector(MI.getOperand(0), Ops); in foldInsertEltToCmpSelect()
2097 auto Vec = B.buildBuildVector(MergeTy, Ops); in foldInsertEltToCmpSelect()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h693 return MIB.buildBuildVector(NewBVTy, NewSrcs).getReg(0); in findValueFromBuildVector()
H A DMachineIRBuilder.h1074 MachineInstrBuilder buildBuildVector(const DstOp &Res,