Home
last modified time | relevance | path

Searched refs:buildBitcast (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPreLegalizerCombiner.cpp198 auto Bitcast = B.buildBitcast({S32}, CvtPk); in applyClampI64ToI16()
H A DAMDGPURegBankLegalizeHelper.cpp174 auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg); in unpackZExt()
182 auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg); in unpackSExt()
189 auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg); in unpackAExt()
H A DAMDGPULegalizerInfo.cpp626 auto Scalar = B.buildBitcast(ScalarTy, BitcastReg); in castBufferRsrcFromV4I32()
654 return B.buildBitcast(VectorTy, Scalar).getReg(0); in castBufferRsrcToV4I32()
3910 B.buildBitcast(Dst, Merge); in legalizeBuildVector()
5636 B.buildBitcast(DstReg, B.buildMergeLikeInstr( in legalizeLaneOp()
5845 Reg = B.buildBitcast(S32, Reg).getReg(0); in handleD16VData()
5859 return B.buildBitcast(LLT::fixed_vector(3, S32), Reg).getReg(0); in handleD16VData()
5864 Reg = B.buildBitcast(LLT::fixed_vector(2, S32), Reg).getReg(0); in handleD16VData()
5897 VData = B.buildBitcast(Ty, VData).getReg(0); in fixStoreSourceType()
6376 AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0); in packImage16bitOpsToDwords()
6777 B.buildBitcast(DstReg, ResultRegs[0]); in legalizeImageIntrinsic()
[all …]
H A DAMDGPURegisterBankInfo.cpp1751 auto Bitcast = B.buildBitcast(S32, Src); in unpackV2S16ToS32()
2127 B.buildBitcast(MI.getOperand(0).getReg(), Vec); in foldInsertEltToCmpSelect()
2913 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl()
3028 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl()
3063 B.buildBitcast(DstReg, InsHi); in applyMappingImpl()
3080 B.buildBitcast(DstReg, InsHi); in applyMappingImpl()
H A DAMDGPUCallLowering.cpp82 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp386 B.buildBitcast(OrigRegs[0], Regs[0]); in buildCopyFromRegs()
449 CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0); in buildCopyFromRegs()
463 CastRegs[I++] = B.buildBitcast(GCDTy, SrcReg).getReg(0); in buildCopyFromRegs()
H A DLegalizerHelper.cpp2079 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); in coerceToScalar()
2132 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); in bitcastSrc()
2139 MIRBuilder.buildBitcast(MO, CastDst); in bitcastDst()
3589 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); in lowerBitcast()
3650 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastExtractVectorElt()
3686 MIRBuilder.buildBitcast(Dst, NewVec); in bitcastExtractVectorElt()
3791 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastInsertVectorElt()
3825 MIRBuilder.buildBitcast(Dst, InsertedElt); in bitcastInsertVectorElt()
3868 MIRBuilder.buildBitcast(SrcScalTy, ConcatMI->getSourceReg(i)) in bitcastConcatVector()
3875 MIRBuilder.buildBitcast(DstReg, BuildReg); in bitcastConcatVector()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp246 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
267 MIB.buildBitcast(Def, Source); in insertBitcasts()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1953 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
1957 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
2082 Val = MIRBuilder.buildBitcast(VTy, Val).getReg(0); in legalizeCTPOP()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h724 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) { in buildBitcast() function