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Searched refs:brtarget (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td95 (BCOND brtarget:$imm, condVal)>;
99 (BCONDA brtarget:$imm, condVal)>;
103 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
107 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
111 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
115 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
119 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
123 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
127 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
131 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
H A DSparcInstrInfo.td211 def brtarget : Operand<OtherVT> {
896 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
945 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
948 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
985 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
988 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
1021 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
1024 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips64r6InstrInfo.td83 class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
84 class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
85 class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
86 class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
87 class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
88 class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
89 class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
90 class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
91 class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
92 class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
H A DMips32r6InstrInfo.td427 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
448 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
449 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
450 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
451 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
453 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
454 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
456 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
457 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
459 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
[all …]
H A DMipsInstrInfo.td839 def brtarget : Operand<OtherVT> {
1549 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
2000 (ins brtarget:$tgt, brtarget:$baltgt), []> {
2005 (ins brtarget:$tgt), []> {
2011 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []> {
2016 (ins GPR32Opnd:$src, brtarget:$tgt), []> {
2225 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>,
2227 def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
2229 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>,
2231 def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>,
[all …]
H A DMips64InstrInfo.td266 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>,
268 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>,
270 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>,
272 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>,
274 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>,
276 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>,
431 PseudoSE<(outs GPR64Opnd:$dst), (ins brtarget:$tgt), []>, GPR_64 {
436 PseudoSE<(outs GPR64Opnd:$dst), (ins GPR64Opnd:$src, brtarget:$tgt), []>,
445 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>,
512 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
[all …]
H A DMipsInstrFPU.td730 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
732 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
734 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
736 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
915 (BCTrue FCC0, brtarget:$offset), 1>;
918 (BCFalse FCC0, brtarget:$offset), 1>;
H A DMips16InstrInfo.td54 FI16<op, (outs), (ins brtarget:$imm11),
112 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm8),
151 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
214 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm16),
265 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
277 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
H A DMicroMipsInstrInfo.td1413 (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
1416 (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
H A DMipsDSPInstrInfo.td887 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
H A DMipsMSAInstrInfo.td1397 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td276 (ins AR:$s, AR:$t, brtarget:$target),
287 (ins AR:$s, b4const:$imm, brtarget:$target),
300 (ins AR:$s, b4constu:$imm, brtarget:$target),
313 (ins AR:$s, brtarget:$target),
342 (ins AR:$s, AR:$t, brtarget:$target),
351 (ins AR:$s, AR:$t, brtarget:$target),
360 (ins AR:$s, AR:$t, brtarget:$target),
369 (ins AR:$s, AR:$t, brtarget:$target),
378 (ins AR:$s, AR:$t, brtarget:$target),
387 (ins AR:$s, AR:$t, brtarget:$target),
[all …]
H A DXtensaOperands.td184 def brtarget : Operand<OtherVT> {
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td72 def brtarget : Operand<OtherVT> {
189 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
205 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
221 (ins brtarget:$BrDst),
233 (ins GPR32:$dst, GPR32:$src, brtarget:$BrDst),
249 (ins GPR32:$dst, i32imm:$imm, brtarget:$BrDst),
628 (ins brtarget:$BrDst),
640 (ins brtarget:$BrDst),
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td180 def brtarget : Operand<OtherVT>;
274 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
276 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
637 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
639 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600Instructions.td1383 (ins brtarget:$target, R600_Predicate_Bit:$p),
1390 (ins brtarget:$target),
1567 (ins brtarget:$target, rci:$src0),
1571 (ins brtarget:$target, rcf:$src0),
1597 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
H A DSIInstructions.td435 (ins SReg_1:$vcc, brtarget:$target),
442 (outs SReg_1:$dst), (ins SReg_1:$vcc, brtarget:$target),
452 (ins SReg_1:$src, brtarget:$target), [], 1, 1> {
460 (ins brtarget:$target), [], 1> {
467 (outs), (ins SReg_1:$saved, brtarget:$target),
H A DAMDGPUInstructions.td165 def brtarget : Operand<OtherVT>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrOperands.td170 def brtarget : BranchTargetOperand<OtherVT>;
H A DX86InstrCompiler.td231 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp4875 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; in DecodeThumb2BCCInstruction() local
4876 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; in DecodeThumb2BCCInstruction()
4877 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; in DecodeThumb2BCCInstruction()
4878 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; in DecodeThumb2BCCInstruction()
4879 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; in DecodeThumb2BCCInstruction()
4881 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) in DecodeThumb2BCCInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZOperands.td565 // Variants of brtarget for use with branch prediction preload.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td4006 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
5643 (ins GPRlr:$tc, brtarget:$target),
5653 (ins rGPR:$tc, brtarget:$target),
5661 (ins rGPR:$tc, rGPR:$elts, brtarget:$target),
5667 t2PseudoInst<(outs), (ins GPRlr:$tc, brtarget:$target),
5675 t2PseudoInst<(outs GPRlr:$Rm), (ins GPRlr:$tc, brtarget:$target),
H A DARMInstrInfo.td560 // FIXME: rename brtarget to t2_brtarget
561 def brtarget : Operand<OtherVT> {
5024 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
5030 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td35 def brtarget : Operand<OtherVT>;
3789 def CBranch : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
3793 def CBranchOther : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
3797 def GOTO : NVPTXInst<(outs), (ins brtarget:$target),