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Searched refs:bitsLT (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp106 else if (Src.getValueType().bitsLT(MVT::i32)) in EmitSpecializedLibcall()
H A DARMISelLowering.cpp162 assert(Arg.ArgVT.bitsLT(MVT::i32)); in handleCMSEValue()
2291 VA.getLocVT().isScalarInteger() && Arg.ArgVT.bitsLT(MVT::i32)) in LowerCallResult()
4640 RegVT.isScalarInteger() && Arg.ArgVT.bitsLT(MVT::i32)) in LowerFormalArguments()
8253 if (SrcEltTy.bitsLT(SmallestEltTy)) in ReconstructShuffle()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h290 bool bitsLT(EVT VT) const { in bitsLT() function
H A DTargetLowering.h4813 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h407 bool bitsLT(MVT VT) const { in bitsLT() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1206 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
1324 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1549 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
H A DSIISelLowering.cpp2025 VT.bitsLT(MemVT)) { in convertArgType()
3018 if (MemVT.bitsLT(NewArg.getSimpleValueType())) in LowerFormalArguments()
6423 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
10155 if (VT.bitsLT(Op.getValueType())) in getLoadExtOrTrunc()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1604 if (VT.bitsLT(Op.getValueType())) in getVPZExtOrTrunc()
3004 if (LegalSVT.bitsLT(SVT)) in getSplatValue()
5862 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); in foldCONCAT_VECTORS()
5984 assert(N1.getValueType().bitsLT(VT) && "Invalid fpext node, dst < src!"); in getNode()
6009 assert(N1.getValueType().bitsLT(VT) && "Invalid sext node, dst < src!"); in getNode()
6030 assert(N1.getValueType().bitsLT(VT) && "Invalid zext node, dst < src!"); in getNode()
6068 assert(N1.getValueType().bitsLT(VT) && "Invalid anyext node, dst < src!"); in getNode()
6106 if (N1.getOperand(0).getValueType().getScalarType().bitsLT( in getNode()
6691 if (LegalSVT.bitsLT(VT.getScalarType())) in FoldConstantArithmetic()
8210 if (VT.bitsLT(LargestVT)) { in getMemsetStores()
[all …]
H A DLegalizeTypesGeneric.cpp224 assert(OldEltVT.bitsLT(OldVT) && "Result type smaller then element type!"); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DFastISel.cpp391 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
1911 if (DstVT.bitsLT(SrcVT)) in selectOperator()
H A DLegalizeDAG.cpp1532 MemVT.bitsLT(Node->getOperand(0).getValueType()); in ExpandVectorBuildThroughStack()
1788 (SlotVT.bitsLT(DestVT) && in EmitStackConvert()
1818 assert(SlotVT.bitsLT(DestVT) && "Unknown extension!"); in EmitStackConvert()
3488 if (NewEltVT.bitsLT(EltVT)) { in ExpandNode()
5640 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
5686 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
H A DSelectionDAGBuilder.cpp266 ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
279 if (ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
293 if (ValueVT.bitsLT(Val.getValueType())) { in getCopyFromParts()
314 ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
461 } else if (ValueVT.bitsLT(PartEVT)) { in getCopyFromPartsVector()
484 assert(ValueSVT.bitsLT(PartEVT) && "Unexpected types"); in getCopyFromPartsVector()
7974 if (CountVT.bitsLT(VT)) { in visitIntrinsicCall()
H A DDAGCombiner.cpp6480 if (LdStMemVT.bitsLT(MemVT)) in isLegalNarrowLdSt()
13936 if (SrcVT.bitsLT(VT) && VT.isVector()) { in visitZERO_EXTEND()
14356 EVT MinAssertVT = AssertVT.bitsLT(BigA_AssertVT) ? AssertVT : BigA_AssertVT; in visitAssertExt()
14371 if (AssertVT.bitsLT(BigA_AssertVT)) { in visitAssertExt()
14692 ExtVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) in visitSIGN_EXTEND_INREG()
14949 if (N0.getOperand(0).getValueType().bitsLT(VT)) in visitTRUNCATE()
14966 if (ExtVT.bitsLT(VT) && TLI.preferSextInRegOfTruncate(VT, SrcVT, ExtVT)) { in visitTRUNCATE()
17990 if (VT.bitsLT(In.getValueType())) in visitFP_EXTEND()
21410 if (MemVT.bitsLT(VT)) { // Is truncating store in visitATOMIC_STORE()
22345 if (ResultVT.bitsLT(VecEltVT)) in scalarizeExtractedVectorLoad()
[all …]
H A DTargetLowering.cpp4871 else if (Op0.getValueType().bitsLT(VT)) in SimplifySetCC()
10231 if (VT.bitsLT(MVT::i32)) { in lowerCmpEqZeroToCtlzSrl()
11029 if (RType.bitsLT(Overflow.getValueType())) in expandMULO()
H A DLegalizeVectorTypes.cpp619 if (BoolVT.bitsLT(CondVT)) in ScalarizeVecRes_VSELECT()
3182 if (N->getValueType(0).bitsLT( in SplitVectorOperand()
H A DLegalizeIntegerTypes.cpp5868 if (OpVT.bitsLT(NOutVTElem)) { in PromoteIntRes_BUILD_VECTOR()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1110 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1594 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
H A DCodeGenPrepare.cpp1479 if (SrcVT.bitsLT(DstVT)) in OptimizeNoopCopyExpression()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td71 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32);
H A DMipsISelLowering.cpp4057 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp994 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
H A DX86FastISel.cpp3684 if (DstVT.bitsLT(SrcVT)) in fastSelectInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5483 if (IntVT.bitsLT(VT)) in lowerCTLZ_CTTZ_ZERO_UNDEF()
8253 assert(DstEltVT.bitsLT(SrcEltVT) && isPowerOf2_64(DstEltVT.getSizeInBits()) && in lowerVectorTruncLike()
8799 if (OpVT.bitsLT(XLenVT)) { in lowerVectorIntrinsicScalars()
9040 if (OpVT.bitsLT(XLenVT)) { in promoteVCIXScalar()
12844 if (VT.bitsLT(XLenVT)) { in ReplaceNodeResults()
14127 if (ResultVT.bitsLT(VT.getVectorElementType())) { in narrowIndex()
16375 if (IndexVT.getVectorElementType().bitsLT(XLenVT)) { in legalizeScatterGatherIndexType()
17511 if (M1VT.bitsLT(VT)) { in PerformDAGCombine()
17536 if (M1VT.bitsLT(VecVT)) { in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4966 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1599 dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLT(MVT::i32)) in lowerUINT_TO_FP()

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