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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DMSP430Target.def203 // With 16-bit hardware multiplier
204 MSP430_MCU_FEAT("msp430c336", "16bit")
205 MSP430_MCU_FEAT("msp430c337", "16bit")
206 MSP430_MCU_FEAT("msp430cg4616", "16bit")
207 MSP430_MCU_FEAT("msp430cg4617", "16bit")
208 MSP430_MCU_FEAT("msp430cg4618", "16bit")
209 MSP430_MCU_FEAT("msp430cg4619", "16bit")
210 MSP430_MCU_FEAT("msp430e337", "16bit")
211 MSP430_MCU_FEAT("msp430f147", "16bit")
212 MSP430_MCU_FEAT("msp430f148", "16bit")
[all …]
H A DBuiltinsRISCV.td26 def orc_b_64 : RISCVBuiltin<"uint64_t(uint64_t)", "zbb,64bit">;
28 def clz_64 : RISCVBuiltin<"unsigned int(uint64_t)", "zbb|xtheadbb,64bit">;
30 def ctz_64 : RISCVBuiltin<"unsigned int(uint64_t)", "zbb,64bit">;
36 def clmul_64 : RISCVBuiltin<"uint64_t(uint64_t, uint64_t)", "zbc|zbkc,64bit">;
37 def clmulh_32 : RISCVBuiltin<"unsigned int(unsigned int, unsigned int)", "zbc|zbkc,32bit">;
38 def clmulh_64 : RISCVBuiltin<"uint64_t(uint64_t, uint64_t)", "zbc|zbkc,64bit">;
39 def clmulr_32 : RISCVBuiltin<"unsigned int(unsigned int, unsigned int)", "zbc,32bit">;
40 def clmulr_64 : RISCVBuiltin<"uint64_t(uint64_t, uint64_t)", "zbc,64bit">;
45 let Features = "zbkx,32bit" in {
48 } // Features = "zbkx,32bit"
[all …]
/freebsd/sys/compat/linuxkpi/common/include/linux/
H A Dbitops.h128 int bit; in find_first_bit()
130 for (bit = 0; size >= BITS_PER_LONG; in find_first_bit()
131 size -= BITS_PER_LONG, bit += BITS_PER_LONG, addr++) { in find_first_bit()
134 return (bit + __ffsl(*addr)); in find_first_bit()
139 bit += __ffsl(mask); in find_first_bit()
141 bit += size; in find_first_bit()
143 return (bit); in find_first_bit()
150 int bit; in find_first_zero_bit()
152 for (bit = 0; size >= BITS_PER_LONG; in find_first_zero_bit()
153 size -= BITS_PER_LONG, bit in find_first_zero_bit()
127 int bit; find_first_bit() local
149 int bit; find_first_zero_bit() local
172 int bit; find_last_bit() local
198 int bit; find_next_bit() local
238 int bit; find_next_zero_bit() local
291 test_and_clear_bit(long bit,volatile unsigned long * var) test_and_clear_bit() argument
306 __test_and_clear_bit(long bit,volatile unsigned long * var) __test_and_clear_bit() argument
321 test_and_set_bit(long bit,volatile unsigned long * var) test_and_set_bit() argument
336 __test_and_set_bit(long bit,volatile unsigned long * var) __test_and_set_bit() argument
401 for_each_set_bit(bit,addr,size) global() argument
406 for_each_clear_bit(bit,addr,size) global() argument
[all...]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
63 vdig : regulator VDIG (register 32, bit 9)
64 vgen : regulator VGEN (register 32, bit 12)
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dispell17 >2 leshort 0x00 8-bit, no capitalization, 26 flags
18 >2 leshort 0x01 7-bit, no capitalization, 26 flags
19 >2 leshort 0x02 8-bit, capitalization, 26 flags
20 >2 leshort 0x03 7-bit, capitalization, 26 flags
21 >2 leshort 0x04 8-bit, no capitalization, 52 flags
22 >2 leshort 0x05 7-bit, no capitalization, 52 flags
23 >2 leshort 0x06 8-bit, capitalization, 52 flags
24 >2 leshort 0x07 7-bit, capitalization, 52 flags
25 >2 leshort 0x08 8-bit, no capitalization, 128 flags
26 >2 leshort 0x09 7-bit, no capitalization, 128 flags
[all …]
H A Dmach9 # if set, it's for the 64-bit version of the architecture
10 # yes, this is separate from the low-order magic number bit
11 # it's also separate from the "64-bit libraries" bit in the
20 # 32-bit ABIs.
153 # 64-bit ABIs.
155 >>0 belong&0x00ffffff 0 64-bit architecture=%d
156 >>0 belong&0x00ffffff 1 64-bit architecture=%d
157 >>0 belong&0x00ffffff 2 64-bit architecture=%d
158 >>0 belong&0x00ffffff 3 64-bit architecture=%d
159 >>0 belong&0x00ffffff 4 64-bit architecture=%d
[all …]
H A Ddyadic21 >>>1 byte 0x01 component file 32-bit non-journaled non-checksummed
27 >>>>7 byte&0x28 0x00 32-bit
28 >>>>7 byte&0x28 0x20 64-bit
36 >>>1 byte 0x08 mapped file 32-bit
37 >>>1 byte 0x09 component file 64-bit non-journaled non-checksummed
38 >>>1 byte 0x0a mapped file 64-bit
39 >>>1 byte 0x0b component file 32-bit level 1 journaled non-checksummed
40 >>>1 byte 0x0c component file 64-bit level 1 journaled non-checksummed
41 >>>1 byte 0x0d component file 32-bit level 1 journaled checksummed
42 >>>1 byte 0x0e component file 64-bit level 1 journaled checksummed
[all …]
/freebsd/contrib/jemalloc/include/jemalloc/internal/
H A Dbitmap.h195 bitmap_get(bitmap_t *bitmap, const bitmap_info_t *binfo, size_t bit) { in bitmap_get() argument
199 assert(bit < binfo->nbits); in bitmap_get()
200 goff = bit >> LG_BITMAP_GROUP_NBITS; in bitmap_get()
202 return !(g & (ZU(1) << (bit & BITMAP_GROUP_NBITS_MASK))); in bitmap_get()
206 bitmap_set(bitmap_t *bitmap, const bitmap_info_t *binfo, size_t bit) { in bitmap_set() argument
211 assert(bit < binfo->nbits); in bitmap_set()
212 assert(!bitmap_get(bitmap, binfo, bit)); in bitmap_set()
213 goff = bit >> LG_BITMAP_GROUP_NBITS; in bitmap_set()
216 assert(g & (ZU(1) << (bit & BITMAP_GROUP_NBITS_MASK))); in bitmap_set()
217 g ^= ZU(1) << (bit & BITMAP_GROUP_NBITS_MASK); in bitmap_set()
[all …]
/freebsd/contrib/sendmail/include/sm/
H A Dbitops.h34 # define _BITWORD(bit) (((unsigned char)(bit) / (BYTEBITS * sizeof (int))) & BITMAPMAX) argument
35 # define _BITBIT(bit) ((unsigned int)1 << ((unsigned char)(bit) % (BYTEBITS * sizeof (int)))) argument
40 # define bitidx(bit) ((unsigned int) (bit) & 0xff) argument
43 # define bitnset(bit, map) ((map)[_BITWORD(bit)] & _BITBIT(bit)) argument
46 # define setbitn(bit, map) (map)[_BITWORD(bit)] |= _BITBIT(bit) argument
49 # define clrbitn(bit, map) (map)[_BITWORD(bit)] &= ~_BITBIT(bit) argument
55 # define bitset(bit, word) (((word) & (bit)) != 0) argument
/freebsd/sys/contrib/device-tree/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) argument
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) argument
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) argument
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) argument
53 #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) argument
87 #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) argument
88 #define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) argument
112 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) argument
113 #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) argument
H A Dstm32h7-rcc.h17 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) argument
28 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) argument
37 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) argument
56 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) argument
62 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) argument
90 #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) argument
99 #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) argument
118 #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) argument
134 #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) argument
/freebsd/sys/powerpc/fpu/
H A Dfpu_sqrt.c190 u_int bit, q, tt; in fpu_sqrt() local
285 bit = FP_1; in fpu_sqrt()
288 q = bit; in fpu_sqrt()
289 x0 -= bit; in fpu_sqrt()
290 y0 = bit << 1; in fpu_sqrt()
293 while ((bit >>= 1) != 0) { /* for remaining bits in q0 */ in fpu_sqrt()
295 t0 = y0 | bit; /* t = y + bit */ in fpu_sqrt()
298 q |= bit; /* q += bit */ in fpu_sqrt()
299 y0 |= bit << 1; /* y += bit << 1 */ in fpu_sqrt()
311 bit = 1 << 31; in fpu_sqrt()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td17 field bit SALU = 0;
18 field bit VALU = 0;
21 field bit SOP1 = 0;
22 field bit SOP2 = 0;
23 field bit SOPC = 0;
24 field bit SOPK = 0;
25 field bit SOPP = 0;
28 field bit VOP1 = 0;
29 field bit VOP2 = 0;
30 field bit VOPC = 0;
[all …]
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod24 =item bit #4 denoting presence of Time-Stamp Counter.
26 =item bit #19 denoting availability of CLFLUSH instruction;
28 =item bit #20, reserved by Intel, is used to choose among RC4 code paths;
30 =item bit #23 denoting MMX support;
32 =item bit #24, FXSR bit, denoting availability of XMM registers;
34 =item bit #25 denoting SSE support;
36 =item bit #26 denoting SSE2 support;
38 =item bit #28 denoting Hyperthreading, which is used to distinguish
41 =item bit #30, reserved by Intel, denotes specifically Intel CPUs;
43 =item bit #33 denoting availability of PCLMULQDQ instruction;
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DM68k.def6 ELF_RELOC(R_68K_32, 1) /* Direct 32 bit */
7 ELF_RELOC(R_68K_16, 2) /* Direct 16 bit */
8 ELF_RELOC(R_68K_8, 3) /* Direct 8 bit */
9 ELF_RELOC(R_68K_PC32, 4) /* PC relative 32 bit */
10 ELF_RELOC(R_68K_PC16, 5) /* PC relative 16 bit */
11 ELF_RELOC(R_68K_PC8, 6) /* PC relative 8 bit */
12 ELF_RELOC(R_68K_GOTPCREL32, 7) /* 32 bit PC relative GOT entry */
13 ELF_RELOC(R_68K_GOTPCREL16, 8) /* 16 bit PC relative GOT entry */
14 ELF_RELOC(R_68K_GOTPCREL8, 9) /* 8 bit PC relative GOT entry */
15 ELF_RELOC(R_68K_GOTOFF32, 10) /* 32 bit GOT offset */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap24xx-clocks.dtsi12 ti,bit-shift = <2>;
26 ti,bit-shift = <6>;
78 ti,bit-shift = <23>;
94 ti,bit-shift = <6>;
103 ti,bit-shift = <6>;
132 ti,bit-shift = <2>;
142 ti,bit-shift = <6>;
152 ti,bit-shift = <5>;
180 ti,bit-shift = <3>;
196 ti,bit-shift = <7>;
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/freebsd/cddl/contrib/opensolaris/cmd/dtrace/test/cmd/baddof/
H A Dbaddof.c58 int bit, i; in corrupt() local
70 for (bit = 0; bit < len * 8; bit++) { in corrupt()
71 saved = buf[bit / 8]; in corrupt()
72 buf[bit / 8] ^= (1 << (bit % 8)); in corrupt()
74 if ((bit % 100) == 0) in corrupt()
75 printf("%d\n", bit); in corrupt()
81 buf[bit / 8] = saved; in corrupt()
94 buf[bit / 8] = saved; in corrupt()
112 buf[bit / 8] = saved; in corrupt()
125 bit = lrand48() % (len * 8); in corrupt()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dfsl-sec2.txt16 (EUs) are available. It's a single 32-bit cell. EU information
20 bit 0 = reserved - should be 0
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
22 bit 2 = set if SEC has the DES/3DES EU (DEU)
23 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
24 bit 4 = set if SEC has the random number generator EU (RNG)
25 bit 5 = set if SEC has the public key EU (PKEU)
26 bit 6 = set if SEC has the AES EU (AESU)
27 bit 7 = set if SEC has the Kasumi EU (KEU)
28 bit 8 = set if SEC has the CRC EU (CRCU)
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCVXsf.td22 // Input: (bit<27-26>, bit<24-20>, scalar_in, vl) or
23 class RISCVSFCustomVC_X<bit HasSE, bit ImmScalar>
26 … !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>], // bit<27-26> and bit<24-20>
35 // Input: (bit<27-26>, bit<24-20>, bit<11-7>, scalar_in, sew, log2lmul, vl)
36 class RISCVSFCustomVC_X_WO_Suffix<bit ImmScalar>
42 … ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], // bit<27-26>, bit<24-20>, bit<11-7>, sew, log2lmul
50 // Input: (bit<27-26>, vector_in, vector_in/scalar_in, vl) or
51 // (bit<27-26>, bit<11-7>, vector_in, vector_in/scalar_in, vl)
52 class RISCVSFCustomVC_XV<bit HasDst, bit HasSE, bit ImmScalar>
57 … !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>], // bit<27-26>
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide
17 def WriteIDiv32 : SchedWrite; // 32-bit divide on RV64I
18 def WriteIRem : SchedWrite; // 32-bit or 64-bit remainder
19 def WriteIRem32 : SchedWrite; // 32-bit remainder on RV64I
[all …]
/freebsd/contrib/wpa/src/utils/
H A Dbitfield.c40 void bitfield_set(struct bitfield *bf, size_t bit) in bitfield_set() argument
42 if (bit >= bf->max_bits) in bitfield_set()
44 bf->bits[bit / 8] |= BIT(bit % 8); in bitfield_set()
48 void bitfield_clear(struct bitfield *bf, size_t bit) in bitfield_clear() argument
50 if (bit >= bf->max_bits) in bitfield_clear()
52 bf->bits[bit / 8] &= ~BIT(bit % 8); in bitfield_clear()
56 int bitfield_is_set(struct bitfield *bf, size_t bit) in bitfield_is_set() argument
58 if (bit >= bf->max_bits) in bitfield_is_set()
60 return !!(bf->bits[bit / 8] & BIT(bit % 8)); in bitfield_is_set()
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-74xx-mmio.txt5 "ti,741g125": for 741G125 (1-bit Input),
6 "ti,741g174": for 741G74 (1-bit Output),
7 "ti,742g125": for 742G125 (2-bit Input),
8 "ti,7474" : for 7474 (2-bit Output),
9 "ti,74125" : for 74125 (4-bit Input),
10 "ti,74175" : for 74175 (4-bit Output),
11 "ti,74365" : for 74365 (6-bit Input),
12 "ti,74174" : for 74174 (6-bit Output),
13 "ti,74244" : for 74244 (8-bit Input),
14 "ti,74273" : for 74273 (8-bit Output),
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DInstructionUtils.h36 static inline uint32_t Bit32(const uint32_t bits, const uint32_t bit) { in Bit32() argument
37 return (bits >> bit) & 1u; in Bit32()
40 static inline uint64_t Bit64(const uint64_t bits, const uint32_t bit) { in Bit64() argument
41 return (bits >> bit) & 1ull; in Bit64()
55 static inline void SetBit32(uint32_t &bits, const uint32_t bit, in SetBit32() argument
57 SetBits32(bits, bit, bit, val); in SetBit32()
73 static inline uint64_t MaskUpToBit(const uint64_t bit) { in MaskUpToBit() argument
74 if (bit >= 63) in MaskUpToBit()
76 return (1ull << (bit + 1ull)) - 1ull; in MaskUpToBit()
89 static inline bool BitIsSet(const uint64_t value, const uint64_t bit) { in BitIsSet() argument
[all …]
/freebsd/lib/libvgl/
H A Dtext.c77 int b, Bpc, Bpl, lin, bit, topbit; in VGLBitmapPutChar() local
83 for(bit = 0; bit < VGLTextFont->Width; bit++) { in VGLBitmapPutChar()
84 b = bit + (-VGLTextFont->Width & 7); in VGLBitmapPutChar()
88 VGLSetXY(Object, (x+topbit-bit), (y+lin), fgcol); in VGLBitmapPutChar()
91 VGLSetXY(Object, (x+lin), (y-topbit+bit), fgcol); in VGLBitmapPutChar()
94 VGLSetXY(Object, (x-topbit+bit), (y-lin), fgcol); in VGLBitmapPutChar()
97 VGLSetXY(Object, (x-lin), (y+topbit-bit), fgcol); in VGLBitmapPutChar()
100 VGLSetXY(Object, (x+lin+topbit-bit), (y+lin+bit), fgcol); in VGLBitmapPutChar()
106 VGLSetXY(Object, (x+topbit-bit), (y+lin), bgcol); in VGLBitmapPutChar()
109 VGLSetXY(Object, (x+lin), (y-topbit+bit), bgcol); in VGLBitmapPutChar()
[all …]

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