| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 76 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass() function in __anondde7a8760111::RegisterBank 404 Bank.addRegisterClass(RC); in run()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 58 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering() 59 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering() 60 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering() 61 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering() 62 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering() 63 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering() 72 addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering() 73 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering() 74 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering() 76 addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering() [all …]
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| H A D | HexagonISelLowering.cpp | 1550 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering() 1551 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering() 1552 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa in HexagonTargetLowering() 1553 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba in HexagonTargetLowering() 1554 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering() 1555 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering() 1556 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering() 1557 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering() 1558 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering() 1559 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/ |
| H A D | DirectXTargetMachine.cpp | 205 addRegisterClass(MVT::i32, &dxil::DXILClassRegClass); in DirectXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 59 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering() 60 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering() 61 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering() 62 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering() 64 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 65 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 66 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 67 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 68 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 69 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 95 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering() 96 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering() 98 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering() 99 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering() 101 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering() 106 addRegisterClass(MVT::f64, V64RegClass); in SITargetLowering() 107 addRegisterClass(MVT::v2f32, V64RegClass); in SITargetLowering() 108 addRegisterClass(MVT::Untyped, V64RegClass); in SITargetLowering() 110 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass); in SITargetLowering() 111 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering() [all …]
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| H A D | R600ISelLowering.cpp | 32 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering() 33 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering() 34 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering() 35 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering() 36 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering() 37 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 40 addRegisterClass(MVT::i32, &CSKY::GPRRegClass); in CSKYTargetLowering() 44 addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass); in CSKYTargetLowering() 46 addRegisterClass(MVT::f32, &CSKY::FPR32RegClass); in CSKYTargetLowering() 49 addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass); in CSKYTargetLowering() 51 addRegisterClass(MVT::f64, &CSKY::FPR64RegClass); in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 85 addRegisterClass(MVT::i32, &VE::I32RegClass); in initRegisterClasses() 86 addRegisterClass(MVT::i64, &VE::I64RegClass); in initRegisterClasses() 87 addRegisterClass(MVT::f32, &VE::F32RegClass); in initRegisterClasses() 88 addRegisterClass(MVT::f64, &VE::I64RegClass); in initRegisterClasses() 89 addRegisterClass(MVT::f128, &VE::F128RegClass); in initRegisterClasses() 93 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses() 94 addRegisterClass(MVT::v256i1, &VE::VMRegClass); in initRegisterClasses() 95 addRegisterClass(MVT::v512i1, &VE::VM512RegClass); in initRegisterClasses()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 106 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering() 109 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering() 127 addRegisterClass(VecTy, &Mips::DSPRRegClass); in MipsSETargetLowering() 162 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass); in MipsSETargetLowering() 203 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsSETargetLowering() 208 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering() 210 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering() 355 addRegisterClass(Ty, RC); in addMSAIntType() 409 addRegisterClass(Ty, RC); in addMSAFloatType()
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| H A D | Mips16ISelLowering.cpp | 133 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in Mips16TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 581 addRegisterClass(MVT::i1, &NVPTX::B1RegClass); in NVPTXTargetLowering() 582 addRegisterClass(MVT::i16, &NVPTX::B16RegClass); in NVPTXTargetLowering() 583 addRegisterClass(MVT::v2i16, &NVPTX::B32RegClass); in NVPTXTargetLowering() 584 addRegisterClass(MVT::v4i8, &NVPTX::B32RegClass); in NVPTXTargetLowering() 585 addRegisterClass(MVT::i32, &NVPTX::B32RegClass); in NVPTXTargetLowering() 586 addRegisterClass(MVT::i64, &NVPTX::B64RegClass); in NVPTXTargetLowering() 587 addRegisterClass(MVT::f32, &NVPTX::B32RegClass); in NVPTXTargetLowering() 588 addRegisterClass(MVT::f64, &NVPTX::B64RegClass); in NVPTXTargetLowering() 589 addRegisterClass(MVT::f16, &NVPTX::B16RegClass); in NVPTXTargetLowering() 590 addRegisterClass(MVT::v2f16, &NVPTX::B32RegClass); in NVPTXTargetLowering() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 59 addRegisterClass(MVT::i64, &BPF::GPRRegClass); in BPFTargetLowering() 61 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); in BPFTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 127 addRegisterClass(XLenVT, &RISCV::GPRRegClass); in RISCVTargetLowering() 130 addRegisterClass(MVT::f16, &RISCV::FPR16RegClass); in RISCVTargetLowering() 132 addRegisterClass(MVT::bf16, &RISCV::FPR16RegClass); in RISCVTargetLowering() 134 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); in RISCVTargetLowering() 136 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); in RISCVTargetLowering() 138 addRegisterClass(MVT::f16, &RISCV::GPRF16RegClass); in RISCVTargetLowering() 140 addRegisterClass(MVT::f32, &RISCV::GPRF32RegClass); in RISCVTargetLowering() 143 addRegisterClass(MVT::f64, &RISCV::GPRRegClass); in RISCVTargetLowering() 145 addRegisterClass(MVT::f64, &RISCV::GPRPairRegClass); in RISCVTargetLowering() 201 addRegisterClass(VT, RC); in RISCVTargetLowering() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 59 addRegisterClass(MVT::i32, &Xtensa::ARRegClass); in XtensaTargetLowering() 62 addRegisterClass(MVT::f32, &Xtensa::FPRRegClass); in XtensaTargetLowering() 66 addRegisterClass(MVT::v1i1, &Xtensa::BRRegClass); in XtensaTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 100 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); in SystemZTargetLowering() 102 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass); in SystemZTargetLowering() 103 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass); in SystemZTargetLowering() 106 addRegisterClass(MVT::f16, &SystemZ::VR16BitRegClass); in SystemZTargetLowering() 107 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass); in SystemZTargetLowering() 108 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass); in SystemZTargetLowering() 110 addRegisterClass(MVT::f16, &SystemZ::FP16BitRegClass); in SystemZTargetLowering() 111 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass); in SystemZTargetLowering() 112 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass); in SystemZTargetLowering() 115 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass); in SystemZTargetLowering() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1587 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering() 1589 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering() 1590 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering() 1591 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering() 1594 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering() 1598 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 48 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering() 49 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 187 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering() 190 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering() 193 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering() 195 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering() 196 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering() 319 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering() 752 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering() 952 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering() 953 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering() 954 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 395 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering() 396 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering() 399 addRegisterClass(MVT::i64x8, &AArch64::GPR64x8ClassRegClass); in AArch64TargetLowering() 405 addRegisterClass(MVT::aarch64mfp8, &AArch64::FPR8RegClass); in AArch64TargetLowering() 406 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering() 407 addRegisterClass(MVT::bf16, &AArch64::FPR16RegClass); in AArch64TargetLowering() 408 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering() 409 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering() 410 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering() 414 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 101 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 60 addRegisterClass(MVT::i8, &M68k::DR8RegClass); in M68kTargetLowering() 61 addRegisterClass(MVT::i16, &M68k::XR16RegClass); in M68kTargetLowering() 62 addRegisterClass(MVT::i32, &M68k::XR32RegClass); in M68kTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 39 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); in AVRTargetLowering() 40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 181 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering() 182 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering() 183 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering() 185 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering() 646 addRegisterClass(MVT::f16, Subtarget.hasAVX512() ? &X86::FR16XRegClass in X86TargetLowering() 648 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass in X86TargetLowering() 650 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass in X86TargetLowering() 733 addRegisterClass(MVT::f32, &X86::FR32RegClass); in X86TargetLowering() 735 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering() 765 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 75 addRegisterClass(MVT::i32, &Lanai::GPRRegClass); in LanaiTargetLowering()
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