| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoZclsd.td | 22 let RenderMethod = "addRegOperands";
33 let RenderMethod = "addRegOperands";
|
| H A D | RISCVInstrInfoZa.td | 25 let RenderMethod = "addRegOperands";
32 let RenderMethod = "addRegOperands";
|
| H A D | RISCVInstrInfoD.td | 40 let RenderMethod = "addRegOperands";
47 let RenderMethod = "addRegOperands";
|
| H A D | RISCVInstrInfoZfh.td | 48 let RenderMethod = "addRegOperands";
|
| H A D | RISCVInstrInfoC.td | 749 let RenderMethod = "addRegOperands";
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1066 void addRegOperands(MCInst &Inst, unsigned N) const;
1070 addRegOperands(Inst, N); in addRegOrImmOperands()
1079 addRegOperands(Inst, N); in addRegOrImmWithInputModsOperands()
1099 addRegOperands(Inst, N); in addRegWithInputModsOperands()
2585 void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in AMDGPUOperand
7455 Op.addRegOperands(Inst, 1); in cvtExp()
8777 Op.addRegOperands(Inst, 1); in cvtMubufImpl()
8782 Op.addRegOperands(Inst, 1); in cvtMubufImpl()
9018 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVOP3Interp()
9056 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVINTERP()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 230 let RenderMethod = "addRegOperands";
768 let RenderMethod = "addRegOperands";
817 let RenderMethod = "addRegOperands", ParserMethod="tryParseGPRSeqPair" in {
868 let RenderMethod = "addRegOperands";
1014 let RenderMethod = "addRegOperands";
1055 let RenderMethod = "addRegOperands";
1219 let RenderMethod = "addRegOperands";
1680 let RenderMethod = "addRegOperands";
1738 let RenderMethod = "addRegOperands";
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/AsmParser/ |
| H A D | M68kAsmParser.cpp | 162 void addRegOperands(MCInst &Inst, unsigned N) const;
322 void M68kOperand::addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in M68kOperand
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 193 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 127 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon2e2431ce0111::MSP430Operand
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 305 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonde0c959e0111::SystemZOperand
1349 ZOperand.addRegOperands(Inst, 1); in parseDirectiveInsn()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/AsmParser/ |
| H A D | XtensaAsmParser.cpp | 363 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 134 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon06c44bb20111::AVROperand
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 567 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.td | 44 let RenderMethod = "addRegOperands";
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 385 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
418 addRegOperands(Inst, N); in addsgp10ConstOperands()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 399 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/ |
| H A D | WebAssemblyAsmParser.cpp | 133 void addRegOperands(MCInst &, unsigned) const { in addRegOperands() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 96 let RenderMethod = "addRegOperands";
108 let RenderMethod = "addRegOperands";
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 475 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon944a62760211::VEOperand
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 562 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2600 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon6be9c9a00111::ARMOperand
5848 ((ARMOperand &)*Operands[RegRd]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5858 ((ARMOperand &)*Operands[RegRn]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5860 ((ARMOperand &)*Operands[RegRm]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5938 ((ARMOperand &)*Operands[MnemonicOpsEndInd]).addRegOperands(Inst, 1); // Rt in cvtMVEVMOVQtoDReg()
5940 .addRegOperands(Inst, 1); // Rt2 in cvtMVEVMOVQtoDReg()
5942 .addRegOperands(Inst, 1); // Qd in cvtMVEVMOVQtoDReg()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 400 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonebada3920211::SparcOperand
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.td | 206 let RenderMethod = "addRegOperands", SuperClasses = [MxRegClass]in {
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 460 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|