| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 277 .addDef(Dest) in buildUnalignedLoad()
327 .addDef(PseudoMULTuReg) in select()
334 .addDef(I.getOperand(0).getReg()) in select()
369 .addDef(JTIndex) in select()
377 .addDef(DestAddress) in select()
386 .addDef(Dest) in select()
398 .addDef(Dest) in select()
477 .addDef(ImplDef); in select()
514 .addDef(HILOReg) in select()
522 .addDef(I.getOperand(0).getReg()) in select()
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| H A D | MipsISelLowering.cpp | 4801 .addDef(Temp) in emitLDR_W()
4804 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); in emitLDR_W()
4811 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); in emitLDR_W()
4813 .addDef(LoadHalf) in emitLDR_W()
4818 .addDef(LoadFull) in emitLDR_W()
4822 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); in emitLDR_W()
4848 .addDef(Temp) in emitLDR_D()
4851 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); in emitLDR_D()
4857 .addDef(Lo) in emitLDR_D()
4861 .addDef(Hi) in emitLDR_D()
[all …]
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| H A D | MipsCallLowering.cpp | 123 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
479 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
540 MIB.addDef(Mips::GP, RegState::Implicit); in lowerCall()
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| H A D | MipsSEISelDAGToDAG.cpp | 134 .addDef(Mips::AT_64) in emitMCountABI()
142 .addDef(Mips::AT) in emitMCountABI()
147 .addDef(Mips::SP) in emitMCountABI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVGlobalRegistry.cpp | 90 .addDef(createTypeVReg(MIRBuilder)); in getOpTypeBool()
125 .addDef(createTypeVReg(MIRBuilder)) in getOpTypeInt()
134 .addDef(createTypeVReg(MIRBuilder)) in getOpTypeFloat()
141 .addDef(createTypeVReg(MIRBuilder)); in getOpTypeVoid()
154 .addDef(createTypeVReg(MIRBuilder)) in getOpTypeVector()
248 .addDef(Res) in getOrCreateConstFP()
252 .addDef(Res) in getOrCreateConstFP()
282 .addDef(Res) in getOrCreateConstInt()
287 .addDef(Res) in getOrCreateConstInt()
326 .addDef(Res) in buildConstantInt()
[all …]
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| H A D | SPIRVInstructionSelector.cpp | 373 .addDef(ResVReg) in spvSelect()
557 .addDef(ResVReg) in spvSelect()
646 .addDef(ResVReg) in selectExtInst()
665 .addDef(ResVReg) in selectUnOpWithSrc()
699 .addDef(ResVReg) in selectUnOp()
777 .addDef(ResVReg) in selectLoad()
820 .addDef(ResVReg) in selectStackSave()
865 .addDef(VarReg) in selectMemOperation()
917 .addDef(ResVReg) in selectAtomicRMW()
953 .addDef(ResVReg) in selectUnmergeValues()
[all …]
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| H A D | SPIRVBuiltins.cpp | 581 MIB.addDef(Call->ReturnRegister).addUse(TypeReg);
643 .addDef(Call->ReturnRegister) in buildAtomicLoadInst()
768 .addDef(Tmp) in buildAtomicCompareExchangeInst()
824 .addDef(NegValueReg) in buildAtomicRMWInst()
832 .addDef(Call->ReturnRegister) in buildAtomicRMWInst()
864 .addDef(Call->ReturnRegister) in buildAtomicFloatingRMWInst()
904 MIB.addDef(Call->ReturnRegister).addUse(TypeReg); in buildAtomicFlagInst()
1019 .addDef(Call->ReturnRegister) in generateExtInst()
1044 .addDef(CompareRegister) in generateRelationalInst()
1079 .addDef(Call->ReturnRegister) in generateGroupInst()
[all …]
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| H A D | SPIRVPreLegalizer.cpp | 395 .addDef(Reg) in insertAssignInstr()
419 MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg()); in processInstr()
629 MIRBuilder.buildInstr(SPIRV::OpAsmTargetINTEL).addDef(AsmTargetReg); in insertInlineAsmProcess()
649 .addDef(AsmReg) in insertInlineAsmProcess()
696 .addDef(DefReg) in insertInlineAsmProcess()
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| H A D | SPIRVCallLowering.cpp | 396 .addDef(FuncVReg) in lowerFormalArguments()
408 .addDef(VRegs[i][0]) in lowerFormalArguments()
604 .addDef(ResVReg) in lowerCall()
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| H A D | SPIRVLegalizerInfo.cpp | 331 .addDef(ConvReg) in convertPtrToInt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 232 .addDef(MisspeculatingTaintReg) in insertTrackingCode()
372 .addDef(AArch64::XZR) in insertSPToRegTaintPropagation()
378 .addDef(MisspeculatingTaintReg) in insertSPToRegTaintPropagation()
395 .addDef(TmpReg) in insertRegToSPTaintPropagation()
401 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
407 .addDef(AArch64::SP) in insertRegToSPTaintPropagation()
455 .addDef(Reg) in makeGPRSpeculationSafe()
579 .addDef(DstReg) in expandSpeculationSafeValue()
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| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 233 MIB.addDef(AArch64::SP); in emitStore()
274 MIB.addDef(AArch64::SP); in emitLoad()
353 .addDef(AArch64::FP) in getOrCreateFrameHelper()
368 .addDef(AArch64::X16) in getOrCreateFrameHelper()
615 .addDef(AArch64::FP) in lowerProlog()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.cpp | 795 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); in expandPseudoLogM()
796 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); in expandPseudoLogM()
800 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); in expandPseudoLogM()
801 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); in expandPseudoLogM()
930 .addDef(VMX) in expandPostRAPseudo()
936 .addDef(VMX) in expandPostRAPseudo()
944 .addDef(VMX) in expandPostRAPseudo()
953 .addDef(VMX) in expandPostRAPseudo()
1104 .addDef(MI.getOperand(0).getReg()) in expandGetStackTopPseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 497 .addDef(DestReg) in putConstant()
601 .addDef(ResReg) in insertComparison()
698 .addDef(ResultReg) in selectGlobal()
795 .addDef(ResReg) in selectSelect()
898 .addDef(SExtResult) in select()
947 .addDef(DstReg) in select()
948 .addDef(IgnoredBits) in select()
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| H A D | ARMLowOverheadLoops.cpp | 1466 MIB.addDef(ARM::LR); in RevertLoopEndDec()
1552 MIB.addDef(ARM::LR); in ExpandLoopStart()
1712 MIB.addDef(ARM::LR); in Expand()
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| /freebsd/sys/tools/syscalls/core/ |
| H A D | syscall.lua | 196 function syscall:addDef(line) function
348 if self:addDef(line) then
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 251 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
378 .addDef(X86::AL) in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 163 .addDef(Dst) in repairReg()
195 .addDef(MO.getReg()); in repairReg()
205 UnMergeBuilder.addDef(DefReg); in repairReg()
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| H A D | MachineIRBuilder.cpp | 329 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildConstant()
365 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildFConstant()
853 MIB.addDef(ResultReg); in buildIntrinsic()
1160 return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); in buildBlockAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 350 .addDef(UnusedCarry, RegState::Dead) in selectG_ADD_SUB()
385 .addDef(CarryReg) in selectG_ADD_SUB()
390 .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead) in selectG_ADD_SUB()
998 .addDef(Dst1) in selectDivScale()
1981 MIB.addDef(TmpReg); in selectImageIntrinsic()
1988 MIB.addDef(VDataOut); // vdata output in selectImageIntrinsic()
2056 .addDef(Dst1) in selectDSBvhStackIntrinsic()
3923 .addDef(MRI.createVirtualRegister(DstRegClass)); in buildRegSequence()
5014 .addDef(RSrc2) in buildRSRC()
5017 .addDef(RSrc3) in buildRSRC()
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| H A D | AMDGPURegisterBankInfo.cpp | 676 .addDef(LoLHS) in split64BitValueForMapping()
677 .addDef(HiLHS) in split64BitValueForMapping()
808 .addDef(InitSaveExecReg); in executeInWaterfallLoop()
840 .addDef(PhiExec) in executeInWaterfallLoop()
945 .addDef(NewExec) in executeInWaterfallLoop()
954 .addDef(ExecReg) in executeInWaterfallLoop()
971 .addDef(ExecReg) in executeInWaterfallLoop()
1406 .addDef(LoadParts[i]) // vdata in applyMappingSBufferLoad()
1848 .addDef(DstReg) in buildVCopy()
1858 .addDef(TmpReg0) in buildVCopy()
[all …]
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| H A D | SIShrinkInstructions.cpp | 742 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
743 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 185 MIB.addDef(PhysReg, RegState::Implicit); in assignValueToReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 801 .addDef(Hexagon::D15) in insertEpilogueInBlock()
851 .addDef(Hexagon::D15) in insertEpilogueInBlock()
857 .addDef(Hexagon::D15) in insertEpilogueInBlock()
878 .addDef(Hexagon::D15) in insertEpilogueInBlock()
909 .addDef(SP) in insertAllocframe()
921 .addDef(SP) in insertAllocframe()
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