| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 277 .addDef(Dest) in buildUnalignedLoad()
327 .addDef(PseudoMULTuReg) in select()
334 .addDef(I.getOperand(0).getReg()) in select()
369 .addDef(JTIndex) in select()
377 .addDef(DestAddress) in select()
386 .addDef(Dest) in select()
398 .addDef(Dest) in select()
477 .addDef(ImplDef); in select()
514 .addDef(HILOReg) in select()
522 .addDef(I.getOperand(0).getReg()) in select()
[all …]
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| H A D | MipsISelLowering.cpp | 4971 .addDef(Temp) in emitLDR_W()
4974 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); in emitLDR_W()
4981 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); in emitLDR_W()
4983 .addDef(LoadHalf) in emitLDR_W()
4988 .addDef(LoadFull) in emitLDR_W()
4992 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); in emitLDR_W()
5018 .addDef(Temp) in emitLDR_D()
5021 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); in emitLDR_D()
5027 .addDef(Lo) in emitLDR_D()
5031 .addDef(Hi) in emitLDR_D()
[all …]
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| H A D | MipsCallLowering.cpp | 123 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
477 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
538 MIB.addDef(Mips::GP, RegState::Implicit); in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 589 .addDef(DestReg) in BuildCOPY()
627 .addDef(ResVReg) in spvSelect()
866 .addDef(NewVReg) in spvSelect()
874 .addDef(ResVReg) in spvSelect()
881 .addDef(ResVReg) in spvSelect()
895 .addDef(ResVReg) in spvSelect()
1009 .addDef(ResVReg) in selectExtInst()
1033 .addDef(ResVReg) in selectOpWithSrcs()
1070 .addDef(ResVReg) in selectUnOp()
1171 .addDef(ResVReg) in selectLoad()
[all …]
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| H A D | SPIRVGlobalRegistry.cpp | 147 .addDef(createTypeVReg(MIRBuilder)); in getOpTypeBool()
191 .addDef(createTypeVReg(MIRBuilder)) in getOpTypeInt()
201 .addDef(createTypeVReg(MIRBuilder)) in getOpTypeFloat()
209 .addDef(createTypeVReg(MIRBuilder)); in getOpTypeVoid()
277 .addDef(createTypeVReg(MIRBuilder)) in getOpTypeVector()
314 .addDef(Res) in createConstFP()
318 .addDef(Res) in createConstFP()
367 .addDef(Res) in createConstInt()
371 .addDef(Res) in createConstInt()
376 .addDef(Res) in createConstInt()
[all …]
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| H A D | SPIRVBuiltins.cpp | 636 MIB.addDef(Call->ReturnRegister).addUse(TypeReg);
687 .addDef(Call->ReturnRegister) in buildAtomicLoadInst()
804 .addDef(Tmp) in buildAtomicCompareExchangeInst()
858 .addDef(NegValueReg) in buildAtomicRMWInst()
866 .addDef(Call->ReturnRegister) in buildAtomicRMWInst()
887 .addDef(Call->ReturnRegister) in buildAtomicFloatingRMWInst()
927 MIB.addDef(Call->ReturnRegister).addUse(TypeReg); in buildAtomicFlagInst()
1035 .addDef(Call->ReturnRegister) in buildExtendedBitOpsInst()
1054 .addDef(Call->ReturnRegister) in buildBindlessImageINTELInst()
1071 .addDef(Call->ReturnRegister) in buildTernaryBitwiseFunctionINTELInst()
[all …]
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| H A D | SPIRVEmitNonSemanticDI.cpp | 180 MIB.addDef(StrReg); in emitGlobalDI()
197 .addDef(InstReg) in emitGlobalDI()
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| H A D | SPIRVPreLegalizer.cpp | 186 MIB.buildInstr(TargetOpcode::COPY).addDef(ResVReg).addUse(OpReg); in buildOpBitcast()
189 .addDef(ResVReg) in buildOpBitcast()
458 .addDef(Reg) in insertAssignInstr()
746 MIRBuilder.buildInstr(SPIRV::OpAsmTargetINTEL).addDef(AsmTargetReg); in insertInlineAsmProcess()
768 .addDef(AsmReg) in insertInlineAsmProcess()
799 .addDef(DefReg) in insertInlineAsmProcess()
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| H A D | SPIRVPreLegalizerCombiner.cpp | 91 .addDef(ResultReg) // Result register in applySPIRVDistance()
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| H A D | SPIRVCallLowering.cpp | 443 .addDef(FuncVReg) in lowerFormalArguments()
460 .addDef(ArgReg) in lowerFormalArguments()
717 .addDef(ResVReg) in lowerCall()
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| H A D | SPIRVISelLowering.cpp | 152 .addDef(NewReg) in doInsertBitcast()
621 .addDef(OldResultReg) in insertLogicalCopyOnResult()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 227 .addDef(MisspeculatingTaintReg) in insertTrackingCode()
367 .addDef(AArch64::XZR) in insertSPToRegTaintPropagation()
373 .addDef(MisspeculatingTaintReg) in insertSPToRegTaintPropagation()
390 .addDef(TmpReg) in insertRegToSPTaintPropagation()
396 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
402 .addDef(AArch64::SP) in insertRegToSPTaintPropagation()
450 .addDef(Reg) in makeGPRSpeculationSafe()
574 .addDef(DstReg) in expandSpeculationSafeValue()
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| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 223 MIB.addDef(AArch64::SP); in emitStore()
264 MIB.addDef(AArch64::SP); in emitLoad()
343 .addDef(AArch64::FP) in getOrCreateFrameHelper()
358 .addDef(AArch64::X16) in getOrCreateFrameHelper()
605 .addDef(AArch64::FP) in lowerProlog()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyLateEHPrepare.cpp | 322 MIB.addDef(Def.getReg()); in addCatchRefsAndThrowRefs()
323 MIB.addDef(ExnReg); // Attach the exnref def after extracted values in addCatchRefsAndThrowRefs()
333 .addDef(ExnReg); in addCatchRefsAndThrowRefs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.cpp | 793 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); in expandPseudoLogM()
794 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); in expandPseudoLogM()
798 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); in expandPseudoLogM()
799 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); in expandPseudoLogM()
928 .addDef(VMX) in expandPostRAPseudo()
934 .addDef(VMX) in expandPostRAPseudo()
942 .addDef(VMX) in expandPostRAPseudo()
951 .addDef(VMX) in expandPostRAPseudo()
1102 .addDef(MI.getOperand(0).getReg()) in expandGetStackTopPseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 497 .addDef(DestReg) in putConstant()
601 .addDef(ResReg) in insertComparison()
698 .addDef(ResultReg) in selectGlobal()
795 .addDef(ResReg) in selectSelect()
898 .addDef(SExtResult) in select()
947 .addDef(DstReg) in select()
948 .addDef(IgnoredBits) in select()
1114 .addDef(Reg) in select()
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| /freebsd/sys/tools/syscalls/core/ |
| H A D | syscall.lua | 197 function syscall:addDef(line) function
349 if self:addDef(line) then
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILateBranchLowering.cpp | 162 .addDef(TII->getNamedOperand(MI, AMDGPU::OpName::src0)->getReg()); in expandChainCall()
171 .addDef(ExecReg); in expandChainCall()
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| H A D | SIShrinkInstructions.cpp | 775 .addDef(X) in matchSwap()
776 .addDef(Y) in matchSwap()
789 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
790 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 250 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
377 .addDef(X86::AL) in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 163 .addDef(Dst) in repairReg()
195 .addDef(MO.getReg()); in repairReg()
205 UnMergeBuilder.addDef(DefReg); in repairReg()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 94 MIB.addDef(Reg); in addDefToMIB()
97 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy)); in addDefToMIB()
100 MIB.addDef(MRI.createVirtualRegister(RC)); in addDefToMIB()
103 MIB.addDef(MRI.createVirtualRegister(Attrs)); in addDefToMIB()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 185 MIB.addDef(PhysReg, RegState::Implicit); in assignValueToReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 790 .addDef(Hexagon::D15) in insertEpilogueInBlock()
840 .addDef(Hexagon::D15) in insertEpilogueInBlock()
846 .addDef(Hexagon::D15) in insertEpilogueInBlock()
867 .addDef(Hexagon::D15) in insertEpilogueInBlock()
898 .addDef(SP) in insertAllocframe()
912 .addDef(SP) in insertAllocframe()
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