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Searched refs:ZeroReg (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp123 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
127 TII->get(TargetOpcode::IMPLICIT_DEF), ZeroReg); in runOnMachineFunction()
131 ZeroReg); in runOnMachineFunction()
136 .addReg(ZeroReg) in runOnMachineFunction()
H A DX86FrameLowering.cpp956 ZeroReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64() local
1008 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
1009 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInlineWindowsCoreCLR64()
1010 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInlineWindowsCoreCLR64()
1017 .addReg(ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
H A DMipsSEInstrInfo.cpp87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
182 if (ZeroReg) in copyPhysReg()
183 MIB.addReg(ZeroReg); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
99 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
122 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
H A DMipsAsmPrinter.cpp141 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
142 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td3177 Register ZeroReg, RegisterOperand GPROpnd> {
3185 (Addiu ZeroReg, tglobaladdr:$in)>;
3187 (Addiu ZeroReg, tblockaddress:$in)>;
3189 (Addiu ZeroReg, tjumptable:$in)>;
3191 (Addiu ZeroReg, tconstpool:$in)>;
3193 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3195 (Addiu ZeroReg, texternalsym:$in)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp552 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
553 putConstant(I, ZeroReg, 0); in selectCmp()
558 ZeroReg)) in selectCmp()
564 RHSReg, ZeroReg)) in selectCmp()
H A DARMFastISel.cpp1476 unsigned ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
1479 .addReg(ZeroReg).addImm(1) in SelectCmp()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp934 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8); in LowerINLINEASM() local
935 if (Op.getOperand(Op.getNumOperands() - 1) == ZeroReg || in LowerINLINEASM()
936 Op.getOperand(Op.getNumOperands() - 2) == ZeroReg) { in LowerINLINEASM()
964 Ops.push_back(ZeroReg); in LowerINLINEASM()
1915 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift() local
1916 BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ZeroReg) in insertMultibyteShift()
1940 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), LowByte).addReg(ZeroReg); in insertMultibyteShift()
1958 Regs[I] = std::pair(ZeroReg, 0); in insertMultibyteShift()
1992 ExtByte = ZeroReg; in insertMultibyteShift()
2034 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0); in insertMultibyteShift()
[all …]
H A DAVRExpandPseudoInsts.cpp459 Register ZeroReg = MI.getOperand(2).getReg(); in expand() local
483 .addReg(ZeroReg); in expand()
1494 Register ZeroReg = MI.getOperand(3).getReg(); in expandROLBRd() local
1513 .addReg(ZeroReg); in expandROLBRd()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2782 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); in loadImmediate() local
2802 SrcReg = ZeroReg; in loadImmediate()
2824 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2848 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2880 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
4259 unsigned ZeroReg; in expandDivRem() local
4264 ZeroReg = Mips::ZERO_64; in expandDivRem()
4268 ZeroReg = Mips::ZERO; in expandDivRem()
4292 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4299 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4430 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
4445 MIB.addReg(ZeroReg); in copyGPRRegTuple()
5924 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
5943 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
5957 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
5958 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
6099 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
6101 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
7049 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
7054 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
H A DAArch64InstrInfo.h337 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
H A DAArch64ExpandPseudoInsts.cpp79 unsigned ExtendImm, unsigned ZeroReg,
237 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
270 BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
H A DAArch64ISelDAGToDAG.cpp3785 unsigned ZeroReg; in tryShiftAmountMod() local
3789 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
3793 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
3796 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
3805 unsigned ZeroReg; in tryShiftAmountMod() local
3809 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
3813 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
3816 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
H A DAArch64FastISel.cpp384 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
387 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
4939 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
4942 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg, in selectSDiv()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutorImpl.h1088 uint16_t ZeroReg = readU16(); in executeMatchTable() local
1092 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
1098 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1636 Register ZeroReg = in legalizeIntrinsic() local
1639 {MidReg, ZeroReg}) in legalizeIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2098 MCRegister ZeroReg; in onlyFoldImmediate() local
2101 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2103 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2109 UseMI.getOperand(UseIdx).setReg(ZeroReg); in onlyFoldImmediate()
H A DPPCISelLowering.cpp12242 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary() local
12309 if (ptrA != ZeroReg) { in EmitPartwordAtomicBinary()
12354 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
12397 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
13295 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter() local
13327 if (ptrA != ZeroReg) { in EmitInstrWithCustomInserter()
13384 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
13408 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
H A DPPCISelDAGToDAG.cpp6310 SDValue ZeroReg = in Select() local
6333 Subtarget->isLittleEndian() ? PPC::LVSR : PPC::LVSL, dl, Type, ZeroReg, in Select()
6338 {ZeroReg, N->getOperand(1), N->getOperand(0)}); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp1663 Register ZeroReg = buildZerosVal(ResType, I); in selectSelect() local
1674 .addUse(ZeroReg) in selectSelect()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2292 Register ZeroReg; in applyCombineUnmergeZExtToZExt() local
2294 if (!ZeroReg) in applyCombineUnmergeZExtToZExt()
2295 ZeroReg = Builder.buildConstant(Dst0Ty, 0).getReg(0); in applyCombineUnmergeZExtToZExt()
2296 replaceRegWith(MRI, MI.getOperand(Idx).getReg(), ZeroReg); in applyCombineUnmergeZExtToZExt()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp8816 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion() local
8818 ZeroReg, 0); in convertNonUniformLoopRegion()
8819 HeaderPHIBuilder.addReg(ZeroReg); in convertNonUniformLoopRegion()

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