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Searched refs:ZPR (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td1394 (!cast<Instruction>(Inst # _SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1397 (!cast<Instruction>(Inst # _SXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1400 (!cast<Instruction>(Inst # _UXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1406 (!cast<Instruction>(Inst # _IMM) PPR:$gp, ZPR:$ptrs, ImmTy:$imm)>;
1409 (!cast<Instruction>(Inst) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1412 (!cast<Instruction>(Inst # _SXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1415 (!cast<Instruction>(Inst # _UXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1420 (Inst PPR:$gp, GPR64:$base, ZPR:$offs)>;
1628 (!cast<Instruction>(Inst # _SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>;
1631 (!cast<Instruction>(Inst # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>;
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H A DAArch64RegisterInfo.td1203 def ZPR : ZPRClass<0, 31> {
1217 # Width # ", AArch64::ZPR"
1232 def ZPRAny : ZPRRegOp<"", ZPRAsmOpAny, ElementSizeNone, ZPR>;
1233 def ZPR8 : ZPRRegOp<"b", ZPRAsmOp8, ElementSizeB, ZPR>;
1234 def ZPR16 : ZPRRegOp<"h", ZPRAsmOp16, ElementSizeH, ZPR>;
1235 def ZPR32 : ZPRRegOp<"s", ZPRAsmOp32, ElementSizeS, ZPR>;
1236 def ZPR64 : ZPRRegOp<"d", ZPRAsmOp64, ElementSizeD, ZPR>;
1237 def ZPR128 : ZPRRegOp<"q", ZPRAsmOp128, ElementSizeQ, ZPR>;
1298 class FPRasZPROperand<int Width> : RegisterOperand<ZPR> {
1310 def ZSeqPairs : RegisterTuples<[zsub0, zsub1], [(rotl ZPR, 0), (rotl ZPR, 1)]>;
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H A DAArch64RegisterBanks.td16 def FPRRegBank : RegisterBank<"FPR", [QQQQ, ZPR]>;
H A DSVEInstrFormats.td694 : Pat<(vt (op (pt PPR_3b:$Pg), (vt ZPR:$Zs1), (vt (splat_vector (it immL))))),
1484 …def : Pat<(nxv16i8 (splat_vector (i32 (vector_extract (nxv16i8 ZPR:$vec), sve_elm_idx_extdup_b:$in…
1485 (!cast<Instruction>(NAME # _B) ZPR:$vec, sve_elm_idx_extdup_b:$index)>;
1492 …def : Pat<(VT (splat_vector (SVEType<VT>.EltAsScalar (vector_extract (SVEType<VT>.Packed ZPR:$vec)…
1493 (!cast<Instruction>(NAME # _H) ZPR:$vec, sve_elm_idx_extdup_h:$index)>;
1501 …def : Pat<(VT (splat_vector (SVEType<VT>.EltAsScalar (vector_extract (SVEType<VT>.Packed ZPR:$vec)…
1502 (!cast<Instruction>(NAME # _S) ZPR:$vec, sve_elm_idx_extdup_s:$index)>;
1510 …def : Pat<(VT (splat_vector (SVEType<VT>.EltAsScalar (vector_extract (VT ZPR:$vec), sve_elm_idx_ex…
1511 (!cast<Instruction>(NAME # _D) ZPR:$vec, sve_elm_idx_extdup_d:$index)>;
1525 …<VT>.HalfLength (splat_vector (SVEType<VT>.EltAsScalar (vector_extract (VT ZPR:$vec), sve_elm_idx_…
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H A DAArch64FrameLowering.cpp3186 enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type; enumerator
3193 bool isScalable() const { return Type == PPR || Type == ZPR; } in isScalable()
3282 RPI.Type = RegPairInfo::ZPR; in computeCalleeSaveRegisterPairs()
3326 case RegPairInfo::ZPR: in computeCalleeSaveRegisterPairs()
3528 case RegPairInfo::ZPR: in spillCalleeSavedRegisters()
3628 return c.Type == RegPairInfo::ZPR; in spillCalleeSavedRegisters()
3683 if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) { in spillCalleeSavedRegisters()
3727 auto IsZPR = [](const RegPairInfo &c) { return c.Type == RegPairInfo::ZPR; }; in restoreCalleeSavedRegisters()
3758 case RegPairInfo::ZPR: in restoreCalleeSavedRegisters()
H A DSMEInstrFormats.td51 (ins ZPR:$zn0, ZPR:$zn1), []>, Sched<[]>{
57 (ins ZPR:$zn0, ZPR:$zn1, ZPR:$zn2, ZPR:$zn3), []>, Sched<[]>{
H A DAArch64InstrInfo.td7504 (INS VT128:$Rn, imm:$Immd, (VT128 (EXTRACT_SUBREG ZPR:$Rm, zsub)), SVEIdxTy:$Immn)>;
7511 (VT128 (EXTRACT_SUBREG ZPR:$Rm, zsub)), SVEIdxTy:$Immn),
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmarvell,xenon-sdhci.txt66 Set PHY ZPR value.
69 ZPR is set as 0xF by default if this property is not provided.