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Searched refs:ZEXTLOAD (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1554 enum LoadExtType { NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD }; enumerator
1556 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp776 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
808 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
845 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
877 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
H A DDAGCombiner.cpp6429 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { in isAndLoadExtLoad()
6445 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT)) in isAndLoadExtLoad()
6448 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) in isAndLoadExtLoad()
6569 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) { in SearchForAndLoads()
6572 if (Load->getExtensionType() == ISD::ZEXTLOAD && in SearchForAndLoads()
6983 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) { in visitAND()
6994 ISD::ZEXTLOAD, MLoad->isExpandingLoad()); in visitAND()
7133 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, in visitAND()
7146 case ISD::ZEXTLOAD: in visitAND()
7159 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, in visitAND()
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H A DLegalizeDAG.cpp740 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
753 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
782 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
819 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
901 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, ILoadVT, Chain, in LegalizeLoadOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp50 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) in R600TargetLowering()
58 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
61 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
1345 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
H A DAMDGPUISelLowering.cpp184 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i64, VT, in AMDGPUTargetLowering()
191 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) { in AMDGPUTargetLowering()
202 setLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}, VT, MemVT, in AMDGPUTargetLowering()
1053 return LHS0 && LHS1 && RHSLd && LHS0->getExtensionType() == ISD::ZEXTLOAD && in isDesirableToCommuteWithShift()
1055 RHSLd->getExtensionType() == ISD::ZEXTLOAD; in isDesirableToCommuteWithShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
128 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); in XCoreTargetLowering()
438 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr, in LowerLOAD()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1617 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1678 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand); in HexagonTargetLowering()
1697 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1700 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
3112 LN->getAddressingMode(), ISD::ZEXTLOAD, MVT::i32, dl, LN->getChain(), in LowerLoad()
H A DHexagonISelDAGToDAG.cpp87 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in INITIALIZE_PASS()
143 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in INITIALIZE_PASS()
295 IntExt = ISD::ZEXTLOAD; in tryLoadOfLoadIntrinsic()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td946 // cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
1916 return MGN->getExtensionType() == ISD::ZEXTLOAD &&
1923 return MGN->getExtensionType() == ISD::ZEXTLOAD &&
1930 return MGN->getExtensionType() == ISD::ZEXTLOAD &&
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp662 setAtomicLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT, MemVT, in initActions()
676 setLoadExtAction(ISD::ZEXTLOAD, AVT, VT, Expand); in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td574 return getLoadExtType(N) == ISD::ZEXTLOAD;
611 return ETy == ISD::EXTLOAD || ETy == ISD::ZEXTLOAD;
H A DSystemZISelLowering.cpp303 setAtomicLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i64, in SystemZTargetLowering()
305 setAtomicLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i32, in SystemZTargetLowering()
307 setAtomicLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i16, in SystemZTargetLowering()
364 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
399 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
2532 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) { in adjustSubwordCmp()
2543 ISD::ZEXTLOAD); in adjustSubwordCmp()
2574 case ISD::ZEXTLOAD: in isNaturalMemoryOperand()
2727 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) || in adjustICmpTruncate()
H A DSystemZISelDAGToDAG.cpp1025 Load->getExtensionType() == ISD::ZEXTLOAD) && in tryRISBGZero()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp75 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp325 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
333 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
339 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in WebAssemblyTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp314 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MipsTargetLowering()
505 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Legal); in MipsTargetLowering()
510 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
2751 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); in lowerLOAD()
4469 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp74 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, GRLenVT, in LoongArchTargetLowering()
235 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in LoongArchTargetLowering()
3474 ExtType = ISD::ZEXTLOAD; in checkValueWidth()
3600 if ((ExtType2 != ISD::ZEXTLOAD) && in performSETCCCombine()
6122 LD->getExtensionType() == ISD::ZEXTLOAD)) in isZExtFree()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, MVT::i1, Promote); in CSKYTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFragments.td505 ExtType == ISD::ZEXTLOAD;
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in LanaiTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp67 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp307 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
889 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in PPCTargetLowering()
3814 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
3836 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
7561 return DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, in LowerCall_AIX()
8885 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { in LowerINT_TO_FP()
15013 (LD->getExtensionType() != ISD::ZEXTLOAD && in combineBVZEXTLOAD()
17411 LD->getExtensionType() == ISD::ZEXTLOAD)) in isZExtFree()
18406 case ISD::ZEXTLOAD: in computeMOFlags()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1342 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1382 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Custom); in AArch64TargetLowering()
1385 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Custom); in AArch64TargetLowering()
1407 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1553 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1565 for (auto Op : {ISD::ZEXTLOAD, ISD::SEXTLOAD, ISD::EXTLOAD}) { in AArch64TargetLowering()
2012 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Default); in addTypeForFixedLengthSVE()
3943 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD && in getAArch64Cmp()
6121 if (!isLoadExtLegalOrCustom(ISD::ZEXTLOAD, ExtVT, Ld->getValueType(0))) { in isVectorLoadExtDesirable()
6573 else if (LoadNode->getExtensionType() == ISD::ZEXTLOAD || in LowerLOAD()
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