Lines Matching refs:ZEXTLOAD

1342         setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);  in AArch64TargetLowering()
1382     setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Custom);  in AArch64TargetLowering()
1385     setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Custom);  in AArch64TargetLowering()
1407         setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);  in AArch64TargetLowering()
1553         setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);  in AArch64TargetLowering()
1565     for (auto Op : {ISD::ZEXTLOAD, ISD::SEXTLOAD, ISD::EXTLOAD}) {  in AArch64TargetLowering()
2012       setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Default);  in addTypeForFixedLengthSVE()
3943         cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&  in getAArch64Cmp()
6121     if (!isLoadExtLegalOrCustom(ISD::ZEXTLOAD, ExtVT, Ld->getValueType(0))) {  in isVectorLoadExtDesirable()
6573   else if (LoadNode->getExtensionType() == ISD::ZEXTLOAD ||  in LowerLOAD()
7485         ExtType = ISD::ZEXTLOAD;  in LowerFormalArguments()
18920     if (MaskedLoadOp && (MaskedLoadOp->getExtensionType() == ISD::ZEXTLOAD ||  in performSVEAndCombine()
22053             MLD->getAddressingMode(), ISD::ZEXTLOAD);  in performUnpackCombine()
23351       ExtType = ISD::ZEXTLOAD;  in checkValueWidth()