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Searched refs:XS (Results 1 – 25 of 38) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrKL.td19 NoCD8, XS;
26 NoCD8, XS;
31 NoCD8, XS;
36 NoCD8, XS;
41 NoCD8, XS;
48 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8, XS;
64 …28KL#suffix : I<0xD8, MRM0m, (outs), (ins opaquemem:$src), "aesencwide128kl\t$src", []>, NoCD8, XS;
65 …28KL#suffix : I<0xD8, MRM1m, (outs), (ins opaquemem:$src), "aesdecwide128kl\t$src", []>, NoCD8, XS;
66 …56KL#suffix : I<0xD8, MRM2m, (outs), (ins opaquemem:$src), "aesencwide256kl\t$src", []>, NoCD8, XS;
67 …56KL#suffix : I<0xD8, MRM3m, (outs), (ins opaquemem:$src), "aesdecwide256kl\t$src", []>, NoCD8, XS;
H A DX86InstrSystem.td77 []>, TB, XS, Requires<[In64BitMode]>;
455 def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
477 [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
481 T_MAP7, VEX, XS, NoCD8;
484 []>, T_MAP7, VEX, XS, NoCD8;
528 [(int_x86_wbnoinvd)]>, TB, XS,
539 [(int_x86_incsspd GR32:$src)]>, TB, XS;
541 [(int_x86_incsspq GR64:$src)]>, TB, XS;
547 [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, TB, XS;
550 [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, TB, XS;
[all …]
H A DX86InstrSNP.td20 def PSMASH: I<0x01, MRM_FF, (outs), (ins), "psmash", []>, TB, XS,
39 def RMPADJUST: I<0x01, MRM_FE, (outs), (ins), "rmpadjust", []>, TB, XS,
44 def RMPQUERY: I<0x01, MRM_FD, (outs), (ins), "rmpquery", []>, TB, XS,
H A DX86InstrRAOINT.td39 defm AXOR : RaoInt<"xor">, T8, XS;
46 defm AXOR : RaoInt<"xor", "_EVEX">, EVEX, T_MAP4, XS;
H A DX86InstrVMX.td27 EVEX, NoCD8, T_MAP4, XS, WIG, Requires<[In64BitMode]>;
38 EVEX, NoCD8, T_MAP4, XS, WIG, Requires<[In64BitMode]>;
84 "vmxon\t$vmxon", []>, TB, XS;
H A DX86InstrAVX10.td27 [HasAVX10_2], [HasAVX10_2_512]>, XS;
29 [HasAVX10_2], [HasAVX10_2_512]>, XS;
37 [HasAVX10_2], [HasAVX10_2_512]>, XS;
39 [HasAVX10_2], [HasAVX10_2_512]>, XS;
53 XS, EVEX_CD8<32, CD8VF>;
670 T_MAP5,XS, EVEX_CD8<32, CD8VT1>;
674 REX_W, T_MAP5,XS, EVEX_CD8<32, CD8VT1>;
686 T_MAP5,XS, EVEX_CD8<32, CD8VT1>;
690 T_MAP5,XS,REX_W, EVEX_CD8<32, CD8VT1>;
924 T8, XS, EVEX_CD8<16, CD8VF>;
[all …]
H A DX86InstrAMX.td44 T8, XS;
108 VEX, VVVV, T8, XS;
176 []>, VEX, VVVV, T8, XS;
284 def TDPHBF8PS : AMX_FP8_BASE<0xfd, "tdphbf8ps">, T_MAP5, XS;
374 "ttransposed\t{$src, $dst|$dst, $src}", []>, VEX, T8, XS;
416 []>, VEX, VVVV, T8,XS;
456 []>, VEX, VVVV, T8,XS;
558 []>, TA,XS, EVEX, EVEX_V512;
562 []>, T8,XS, EVEX, VVVV, EVEX_V512;
658 defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>;
H A DX86InstrUtils.td41 class XS { Prefix OpPrefix = XS; }
71 class AVX512XSIi8Base : TB, XS {
485 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
502 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
518 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
567 // SSI - SSE1 instructions with XS prefix.
570 // VSSI - SSE1 instructions with XS prefix in AVX form.
575 : I<o, F, outs, ins, asm, pattern>, TB, XS, Requires<[UseSSE1]>;
578 : Ii8<o, F, outs, ins, asm, pattern>, TB, XS, Requires<[UseSSE1]>;
589 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, TB, XS,
[all …]
H A DX86InstrMisc.td1176 defm LZCNT16 : Lzcnt<0xBD, "lzcnt", ctlz, Xi16, WriteLZCNT, WriteLZCNTLd>, OpSize16, XS;
1177 defm LZCNT32 : Lzcnt<0xBD, "lzcnt", ctlz, Xi32, WriteLZCNT, WriteLZCNTLd>, OpSize32, XS;
1178 defm LZCNT64 : Lzcnt<0xBD, "lzcnt", ctlz, Xi64, WriteLZCNT, WriteLZCNTLd>, XS;
1193 defm TZCNT16 : Lzcnt<0xBC, "tzcnt", cttz, Xi16, WriteTZCNT, WriteTZCNTLd>, OpSize16, XS;
1194 defm TZCNT32 : Lzcnt<0xBC, "tzcnt", cttz, Xi32, WriteTZCNT, WriteTZCNTLd>, OpSize32, XS;
1195 defm TZCNT64 : Lzcnt<0xBC, "tzcnt", cttz, Xi64, WriteTZCNT, WriteTZCNTLd>, XS;
1400 defm PEXT32 : PdepPext<"pext", Xi32, X86pext>, XS, VEX;
1401 defm PEXT64 : PdepPext<"pext", Xi64, X86pext>, XS, REX_W, VEX;
1407 defm PEXT32 : PdepPext<"pext", Xi32, X86pext, "_EVEX">, XS, EVEX;
1408 defm PEXT64 : PdepPext<"pext", Xi64, X86pext, "_EVEX">, XS, REX_W, EVEX;
[all …]
H A DX86InstrSSE.td271 SSEPackedSingle, UseSSE1>, TB, XS;
277 SSEPackedSingle>, TB, XS;
906 TB, XS, VEX, VEX_LIG;
910 TB, XS, VEX, REX_W, VEX_LIG;
923 TB, XS, VEX, VEX_LIG;
927 TB, XS, VEX, REX_W, VEX_LIG;
944 WriteCvtI2SS, SSEPackedSingle>, TB, XS, VEX, VVVV,
947 WriteCvtI2SS, SSEPackedSingle>, TB, XS, VEX, VVVV,
986 WriteCvtSS2I, SSEPackedSingle>, TB, XS, SIMD_EXC;
989 WriteCvtSS2I, SSEPackedSingle>, TB, XS, REX_W, SIMD_EXC;
[all …]
H A DX86InstrArithmetic.td1464 def ADOX32rr : BinOpRRF_RF<0xF6, "adox", Xi32>, T8, XS;
1465 def ADOX64rr : BinOpRRF_RF<0xF6, "adox", Xi64>, T8, XS;
1469 def ADOX32rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi32>, EVEX, T_MAP4, XS;
1470 def ADOX64rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi64>, EVEX, T_MAP4, XS;
1473 def ADOX32rr_ND : BinOpRRF_RF<0x66, "adox", Xi32, null_frag, 1>, XS;
1474 def ADOX64rr_ND : BinOpRRF_RF<0x66, "adox", Xi64, null_frag, 1>, XS;
1480 def ADOX32rm : BinOpRMF_RF<0xF6, "adox", Xi32>, T8, XS;
1481 def ADOX64rm : BinOpRMF_RF<0xF6, "adox", Xi64>, T8, XS;
1485 def ADOX32rm_EVEX : BinOpRMF_RF<0x66, "adox", Xi32>, EVEX, T_MAP4, XS;
1486 def ADOX64rm_EVEX : BinOpRMF_RF<0x66, "adox", Xi64>, EVEX, T_MAP4, XS;
[all …]
H A DX86InstrFormats.td145 def XS : Prefix<2>;
148 // that other instructions with this opcode use PD/XS/XD
H A DX86InstrAVX512.td3438 TB, XS, EVEX_CD8<32, CD8VF>;
3444 TB, XS, REX_W, EVEX_CD8<64, CD8VF>;
3969 VEX_LIG, TB, XS, EVEX_CD8<32, CD8VT1>;
3976 VEX_LIG, T_MAP5, XS, EVEX_CD8<16, CD8VT1>;
4301 []>, T_MAP5, XS, EVEX, VVVV, VEX_LIG,
4310 []>, T_MAP5, XS, EVEX_K, EVEX, VVVV, VEX_LIG,
4317 []>, EVEX_KZ, T_MAP5, XS, EVEX, VVVV, VEX_LIG,
4323 []>, TB, XS, EVEX, VVVV, VEX_LIG,
4332 []>, EVEX_K, TB, XS, EVEX, VVVV, VEX_LIG,
4339 []>, EVEX_KZ, TB, XS, EVEX, VVVV, VEX_LIG,
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DX86RecognizableInstr.cpp209 else if (OpPrefix == X86Local::XS) in insnContext()
222 else if (OpPrefix == X86Local::XS) in insnContext()
244 else if (OpPrefix == X86Local::XS) in insnContext()
258 else if (OpPrefix == X86Local::XS) in insnContext()
272 else if (OpPrefix == X86Local::XS) in insnContext()
288 else if (OpPrefix == X86Local::XS) in insnContext()
300 else if (OpPrefix == X86Local::XS) in insnContext()
316 else if (OpPrefix == X86Local::XS) in insnContext()
329 else if (OpPrefix == X86Local::XS) in insnContext()
345 else if (HasVEX_L && OpPrefix == X86Local::XS) in insnContext()
[all …]
H A DX86RecognizableInstr.h173 enum { PD = 1, XS = 2, XD = 3, PS = 4 }; enumerator
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dsalvator-xs.dtsi65 * (when SW31 is the default setting on Salvator-XS).
67 * r8a77951 with Salvator-XS.
H A Dsalvator-panel-aa104xd12.dts4 * Salvator-X or Salvator-XS board
H A Dsalvator-panel-aa104xd12.dtso4 * Salvator-X or Salvator-XS board
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-xsphy.txt1 MediaTek XS-PHY binding
4 The XS-PHY controller supports physical layer functionality for USB3.1
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrP10.td1342 def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1343 (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>;
1349 def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1350 (PSTXVpc $XS, $ga, 0)>;
1356 def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1357 (PSTXVpc $XS, $ga, 0)>;
1363 def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1364 (PSTXVpc $XS, $ga, 0)>;
1370 def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1371 (PSTXVpc $XS, $ga, 0)>;
[all …]
H A DPPCScheduleP7.td245 (instregex "^XS(N)?M(SUB|ADD)(A|M)(D|S)P$"),
246 (instregex "^XS(NEG|ABS|NABS|ADD|SUB|MUL)(D|S)P(s)?$"),
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86IntelInstPrinter.cpp86 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
202 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) { in printVecCompareInstr()
H A DX86ATTInstPrinter.cpp119 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
228 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) { in printVecCompareInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedXiangShanNanHu.td1 //==- RISCVSchedXiangShanNanHu.td - XS-NanHu Scheduling Defs -*- tablegen -*-=//
/freebsd/usr.sbin/bsdconfig/share/media/
H A Dwlan.subr1283 local XA=" " XC=" " XS=" "
1286 [ "$DIALOG_MENU_WLAN_SHOW_SCAN_RESULTS" ] && XS="X"
1296 '> $msg_show_scan_results' '[$XS]'

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