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Searched refs:XOR (Results 1 – 25 of 165) sorted by relevance

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/freebsd/contrib/unbound/compat/
H A Dchacha_private.h41 #define XOR(v,w) ((v) ^ (w)) macro
46 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
47 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
48 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
49 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
167 x0 = XOR(x0,U8TO32_LITTLE(m + 0)); in chacha_encrypt_bytes()
168 x1 = XOR(x1,U8TO32_LITTLE(m + 4)); in chacha_encrypt_bytes()
169 x2 = XOR(x2,U8TO32_LITTLE(m + 8)); in chacha_encrypt_bytes()
170 x3 = XOR(x3,U8TO32_LITTLE(m + 12)); in chacha_encrypt_bytes()
171 x4 = XOR(x4,U8TO32_LITTLE(m + 16)); in chacha_encrypt_bytes()
[all …]
/freebsd/crypto/openssh/openbsd-compat/
H A Dchacha_private.h43 #define XOR(v,w) ((v) ^ (w)) macro
48 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
49 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
50 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
51 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
169 x0 = XOR(x0,U8TO32_LITTLE(m + 0)); in chacha_encrypt_bytes()
170 x1 = XOR(x1,U8TO32_LITTLE(m + 4)); in chacha_encrypt_bytes()
171 x2 = XOR(x2,U8TO32_LITTLE(m + 8)); in chacha_encrypt_bytes()
172 x3 = XOR(x3,U8TO32_LITTLE(m + 12)); in chacha_encrypt_bytes()
173 x4 = XOR(x4,U8TO32_LITTLE(m + 16)); in chacha_encrypt_bytes()
[all …]
/freebsd/crypto/openssh/
H A Dchacha.c41 #define XOR(v,w) ((v) ^ (w)) macro
46 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
47 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
48 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
49 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
166 x0 = XOR(x0,U8TO32_LITTLE(m + 0)); in chacha_encrypt_bytes()
167 x1 = XOR(x1,U8TO32_LITTLE(m + 4)); in chacha_encrypt_bytes()
168 x2 = XOR(x2,U8TO32_LITTLE(m + 8)); in chacha_encrypt_bytes()
169 x3 = XOR(x3,U8TO32_LITTLE(m + 12)); in chacha_encrypt_bytes()
170 x4 = XOR(x4,U8TO32_LITTLE(m + 16)); in chacha_encrypt_bytes()
[all …]
/freebsd/sys/crypto/chacha20/
H A Dchacha.c43 #define XOR(v,w) ((v) ^ (w)) macro
48 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
49 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
50 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
51 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
191 x0 = XOR(x0,U8TO32_LITTLE(m + 0)); in chacha_encrypt_bytes()
192 x1 = XOR(x1,U8TO32_LITTLE(m + 4)); in chacha_encrypt_bytes()
193 x2 = XOR(x2,U8TO32_LITTLE(m + 8)); in chacha_encrypt_bytes()
194 x3 = XOR(x3,U8TO32_LITTLE(m + 12)); in chacha_encrypt_bytes()
195 x4 = XOR(x4,U8TO32_LITTLE(m + 16)); in chacha_encrypt_bytes()
[all …]
/freebsd/sys/contrib/libsodium/src/libsodium/crypto_stream/chacha20/ref/
H A Dchacha20_ref.c31 #define XOR(v, w) ((v) ^ (w)) macro
37 d = ROTATE(XOR(d, a), 16); \
39 b = ROTATE(XOR(b, c), 12); \
41 d = ROTATE(XOR(d, a), 8); \
43 b = ROTATE(XOR(b, c), 7);
168 x0 = XOR(x0, LOAD32_LE(m + 0)); in chacha20_encrypt_bytes()
169 x1 = XOR(x1, LOAD32_LE(m + 4)); in chacha20_encrypt_bytes()
170 x2 = XOR(x2, LOAD32_LE(m + 8)); in chacha20_encrypt_bytes()
171 x3 = XOR(x3, LOAD32_LE(m + 12)); in chacha20_encrypt_bytes()
172 x4 = XOR(x4, LOAD32_LE(m + 16)); in chacha20_encrypt_bytes()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dmv-xor.txt1 * Marvell XOR engines
10 registers for the XOR engine.
13 The DT node must also contains sub-nodes for each XOR channel that the
14 XOR engine has. Those sub-nodes have the following required
16 - interrupts: interrupt of the XOR channel
20 - dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
21 - dmacap,memset to indicate that the XOR channel is capable of memset operations
22 - dmacap,xor to indicate that the XOR channel is capable of xor operations
23 - dmacap,interrupt to indicate that the XOR channel is capable of
H A Dmv-xor-v2.txt1 * Marvell XOR v2 engines
14 - clocks: Optional reference to the clocks used by the XOR engine.
/freebsd/sys/contrib/libsodium/src/libsodium/crypto_generichash/blake2b/ref/
H A Dblake2b-compress-avx2.h33 #define XOR(a, b) _mm256_xor_si256(a, b) macro
46 d = XOR(d, a); \
49 b = XOR(b, c); \
57 d = XOR(d, a); \
60 b = XOR(b, c); \
129 XOR(LOAD(&blake2b_IV[4]), _mm256_set_epi64x(f1, f0, t1, t0)); \
131 a = XOR(a, c); \
132 b = XOR(b, d); \
133 a = XOR(a, iv0); \
134 b = XOR(b, iv1); \
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-gated-clock.txt45 22 xor0 XOR DMA 0
46 23 xor1 XOR DMA 0
75 22 xor0 XOR 0
78 28 xor1 XOR 1
92 22 xor0 XOR 0
93 28 xor1 XOR 1
115 22 xor0 XOR DMA 0
118 28 xor1 XOR DMA 1
130 22 xor0 XOR DMA 0
150 23 xor0 XOR DMA 0
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h28 XOR = 0x06,
89 case XOR: in lanaiAluCodeToString()
110 .Case("xor", XOR) in stringToLanaiAluCode()
29 XOR = 0x06, global() enumerator
H A DLanaiISelDAGToDAG.cpp233 case ISD::XOR: in isdToLanaiAluCode()
234 return AluCode::XOR; in isdToLanaiAluCode()
/freebsd/sys/contrib/device-tree/Bindings/powerpc/4xx/
H A Dppc440spe-adma.txt1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
4 are specified hereby. These are I2O/DMA, DMA and XOR nodes
60 iii) XOR Accelerator node
66 - interrupts : <interrupt mapping for XOR interrupt source>
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dvdev_raidz_math_avx512f.c102 #define XOR(r...) \ macro
121 #define ZERO(r...) XOR(r, r)
234 if (x & 0x02) { XOR(in, acc); } \
236 if (x & 0x04) { XOR(in, acc); } \
238 if (x & 0x08) { XOR(in, acc); } \
240 if (x & 0x10) { XOR(in, acc); } \
242 if (x & 0x20) { XOR(in, acc); } \
244 if (x & 0x40) { XOR(in, acc); } \
245 if (x & 0x80) { MUL2(in); XOR(in, acc); } \
H A Dvdev_raidz_math_sse2.c88 #define XOR(r...) \ macro
110 #define ZERO(r...) XOR(r, r)
249 if (x & 0x02) { XOR(in, acc); } \
251 if (x & 0x04) { XOR(in, acc); } \
253 if (x & 0x08) { XOR(in, acc); } \
255 if (x & 0x10) { XOR(in, acc); } \
257 if (x & 0x20) { XOR(in, acc); } \
259 if (x & 0x40) { XOR(in, acc); } \
260 if (x & 0x80) { MUL2(in); XOR(in, acc); } \
H A Dvdev_raidz_math_impl.h304 XOR(D, T); \
312 XOR(D, T); \
327 XOR(D, T); \
904 XOR(REC_PQ_Y, REC_PQ_X); in raidz_rec_pq_abd()
908 XOR(REC_PQ_T, REC_PQ_X); in raidz_rec_pq_abd()
1064 XOR(REC_PR_Y, REC_PR_X); in raidz_rec_pr_abd()
1068 XOR(REC_PR_T, REC_PR_X); in raidz_rec_pr_abd()
1228 XOR(REC_QR_Y, REC_QR_X); /* X = R ^ X */ in raidz_rec_qr_abd()
1234 XOR(REC_QR_Y, REC_QR_T); /* X = R ^ X */ in raidz_rec_qr_abd()
1406 XOR(REC_PQR_Y, REC_PQR_X); in raidz_rec_pqr_abd()
[all …]
H A Dvdev_raidz_math_ssse3.c94 #define XOR(r...) \ macro
114 #define ZERO(r...) XOR(r, r)
H A Dvdev_raidz_math_avx2.c93 #define XOR(r...) \ macro
113 #define ZERO(r...) XOR(r, r)
H A Dvdev_raidz_math_avx512bw.c96 #define XOR(r...) \ macro
116 #define ZERO(r...) XOR(r, r)
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCondMov.td201 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
223 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
234 defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
235 defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
246 defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
248 defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
255 defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
259 defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def56 FUSION_OP_SET(AND, ANDC, EQV, NAND, NOR, OR, ORC, XOR, AND8,
62 FUSION_OP_SET(AND, ANDC, EQV, NAND, NOR, OR, ORC, XOR, AND8,
64 FUSION_OP_SET(AND, ANDC, EQV, NAND, NOR, OR, ORC, XOR, AND8,
84 FUSION_OP_SET(XOR, XOR8))
88 FUSION_OP_SET(RLDICR, RLDICR_32), FUSION_OP_SET(XOR, XOR8))
H A DPPCExpandAtomicPseudoInsts.cpp56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy() local
59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def84 HELPER_REDUCTION(XOR, XOR)
108 ADD_BINARY_VVP_OP_COMPACT(XOR) REGISTER_PACKED(VVP_XOR)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h710 XOR, enumerator
1467 return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR; in isBitwiseLogicOp()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h132 R_TYPE_INST(XOR);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp203 BuildMI(LoopMBB, DL, TII->get(LoongArch::XOR), ScratchReg) in doAtomicBinOpExpansion()
227 BuildMI(MBB, DL, TII->get(LoongArch::XOR), ScratchReg) in insertMaskedMerge()
233 BuildMI(MBB, DL, TII->get(LoongArch::XOR), DestReg) in insertMaskedMerge()

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