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Searched refs:X86InstrInfo (Results 1 – 25 of 40) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp84 void X86InstrInfo::anchor() {} in anchor()
86 X86InstrInfo::X86InstrInfo(X86Subtarget &STI) in X86InstrInfo() function in X86InstrInfo
95 X86InstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass()
111 bool X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
161 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) { in isDataInvariant()
228 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) { in isDataInvariantLoad()
411 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const { in getSPAdjust()
462 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op, in isFrameOperand()
676 Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
679 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy); in isLoadFromStackSlot()
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H A DX86SpeculativeLoadHardening.cpp161 const X86InstrInfo *TII = nullptr;
225 const X86InstrInfo &TII) { in splitEdge()
839 getRegClassForUnfoldedLoad(MachineFunction &MF, const X86InstrInfo &TII, in getRegClassForUnfoldedLoad()
1359 if (EnablePostLoadHardening && X86InstrInfo::isDataInvariantLoad(MI) && in tracePredStateThroughBlocksAndHarden()
1415 if (X86InstrInfo::isDataInvariantLoad(MI) && !isEFLAGSDefLive(MI)) { in tracePredStateThroughBlocksAndHarden()
1765 assert(X86InstrInfo::isDataInvariantLoad(InitialMI) && in sinkPostLoadHardenedInst()
1784 if (!X86InstrInfo::isDataInvariantLoad(UseMI) || isEFLAGSDefLive(UseMI)) { in sinkPostLoadHardenedInst()
1788 assert(X86InstrInfo::isDataInvariant(UseMI) && in sinkPostLoadHardenedInst()
1818 if (!X86InstrInfo::isDataInvariant(UseMI) || UseMI.getParent() != MI.getParent() || in sinkPostLoadHardenedInst()
H A DX86Subtarget.h104 X86InstrInfo InstrInfo;
122 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
H A DX86AvoidTrailingCall.cpp84 const X86InstrInfo &TII = *STI.getInstrInfo(); in runOnMachineFunction()
H A DX86FrameLowering.h24 class X86InstrInfo; variable
35 const X86InstrInfo &TII;
H A DX86InsertWait.cpp101 const X86InstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
H A DX86SpeculativeExecutionSideEffectSuppression.cpp18 #include "X86InstrInfo.h"
105 const X86InstrInfo *TII = Subtarget.getInstrInfo(); in runOnMachineFunction()
141 // X86InstrInfo::analyzeBranch method assumes all terminators are grouped in runOnMachineFunction()
H A DX86LoadValueInjectionRetHardening.cpp73 const X86InstrInfo *TII = Subtarget->getInstrInfo(); in runOnMachineFunction()
H A DX86FixupSetCC.cpp55 const X86InstrInfo *TII = nullptr;
H A DX86InstrInfo.td1 //===-- X86InstrInfo.td - Main X86 Instruction Properties --*- tablegen -*-===//
H A DX86ArgumentStackSlotRebase.cpp105 const X86InstrInfo *TII = STI.getInstrInfo(); in runOnMachineFunction()
H A DX86IndirectBranchTracking.cpp53 const X86InstrInfo *TII = nullptr;
H A DX86LowerTileCopy.cpp80 const X86InstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
H A DX86EvexToVex.cpp
H A DX86SchedPredicates.td91 "X86InstrInfo::hasLockPrefix"
H A DX86InstrInfo.h224 class X86InstrInfo final : public X86GenInstrInfo {
241 explicit X86InstrInfo(X86Subtarget &STI);
H A DX86SuppressAPXForReloc.cpp166 const X86InstrInfo *TII = ST.getInstrInfo(); in handleNDDOrNFInstructions()
H A DX86FixupBWInsts.cpp133 const X86InstrInfo *TII = nullptr;
H A DX86FlagsCopyLowering.cpp90 const X86InstrInfo *TII = nullptr;
142 const X86InstrInfo &TII) { in splitBlock()
H A DX86CallFrameOptimization.cpp119 const X86InstrInfo *TII = nullptr;
H A DX86OptimizeLEAs.cpp306 const X86InstrInfo *TII = nullptr;
H A DX86FixupInstTuning.cpp56 const X86InstrInfo *TII = nullptr;
H A DX86AvoidStoreForwardingBlocks.cpp88 const X86InstrInfo *TII = nullptr;
H A DX86DomainReassignment.cpp366 const X86InstrInfo *TII = nullptr;
H A DX86InstrFormats.td115 // Keep in sync with tables in X86InstrInfo.cpp.

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