Home
last modified time | relevance | path

Searched refs:WriteI (Results 1 – 25 of 28) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveInterval.cpp1110 // 1. [begin; WriteI) at the front of LR.
1114 // - LR.begin() <= WriteI <= ReadI <= LR.end().
1125 // and WriteI[-1].start <= LastStart. in print()
1137 OS << " updater with gap = " << (ReadI - WriteI) in print()
1140 for (const auto &S : make_range(LR->begin(), WriteI)) in print()
1184 WriteI = ReadI = LR->begin(); in add()
1193 // First try to close the gap between WriteI and ReadI with spills. in add()
1194 if (ReadI != WriteI) in add()
1197 if (ReadI == WriteI) in add()
1198 ReadI = WriteI in add()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX.td53 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
205 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
209 def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI,
213 def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI,
229 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
233 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
239 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
268 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA53.td62 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
162 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
166 def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
170 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
190 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
196 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
207 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA55.td67 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
219 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
224 def CortexA55ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
228 def CortexA55ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
243 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
247 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
253 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
272 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedThunderX2T99.td419 def : WriteRes<WriteI, [THX2T99I012]> {
425 def : InstRW<[WriteI],
438 def : InstRW<[WriteI], (instrs COPY)>;
585 // NOTE: Handled by WriteI.
602 // NOTE: Handled by WriteLD, WriteI.
723 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRBpost)>;
724 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRDpost)>;
725 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRHpost)>;
726 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRQpost)>;
727 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instr
[all...]
H A DAArch64SchedKryo.td67 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
133 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA64FX.td597 def : WriteRes<WriteI, [A64FXGI2456]> {
601 def : InstRW<[WriteI],
614 def : InstRW<[WriteI], (instrs COPY)>;
749 // NOTE: Handled by WriteI.
765 // NOTE: Handled by WriteLD, WriteI.
884 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRBpost)>;
885 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRDpost)>;
886 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRHpost)>;
887 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRQpost)>;
888 def : InstRW<[A64FXWrite_LDR01, WriteI], (instr
[all...]
H A DAArch64SchedA57.td76 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
134 def : InstRW<[WriteI], (instrs COPY)>;
149 SchedVar<NoSchedPred, [WriteI]>]>;
606 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
612 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
619 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
625 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
635 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
H A DAArch64Schedule.td24 def WriteI : SchedWrite; // ALU
H A DAArch64SchedFalkor.td72 def : WriteRes<WriteI, []> { let Unsupported = 1; }
H A DAArch64SchedCyclone.td129 SchedVar<NoSchedPred, [WriteI]>]>;
153 def : WriteRes<WriteI, [CyUnitI]>;
296 def : InstRW<[WriteI], (instrs ISB)>;
364 def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
H A DAArch64SchedTSV110.td61 def : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; }
124 def : InstRW<[WriteI], (instrs COPY)>;
382 SchedVar<NoSchedPred, [WriteI]>]>;
395 SchedVar<NoSchedPred, [WriteI]>]>;
H A DAArch64SchedThunderX3T110.td679 def : WriteRes<WriteI, [THX3T110I0123]> {
685 def : InstRW<[WriteI],
698 def : InstRW<[WriteI], (instrs COPY)>;
845 // NOTE: Handled by WriteI.
862 // NOTE: Handled by WriteLD, WriteI.
956 def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteI],
970 def : InstRW<[THX3T110Write_4Cyc_LS01_I0123_I0123, WriteI],
H A DAArch64SchedA510.td69 def : WriteRes<WriteI, [CortexA510UnitALU]> { let Latency = 1; } // ALU
245 SchedVar<NoSchedPred, [WriteI]>]>;
282 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedNeoverseN1.td266 def : InstRW<[WriteI], (instrs COPY)>;
303 def : SchedAlias<WriteI, N1Write_1c_1I>;
H A DAArch64InstrFormats.td2290 Sched<[WriteI, ReadI]> {
2322 Sched<[WriteI, ReadI]> {
2350 Sched<[WriteI, ReadI, ReadI]> {
2375 Sched<[WriteI, ReadI]> {
2448 Sched<[WriteI, ReadI, ReadI]> {
2477 Sched<[WriteI, ReadI, ReadI]> {
2697 Sched<[WriteI]> {
2761 Sched<[WriteI, ReadI]> {
2792 Sched<[WriteI, ReadI]> {
2819 Sched<[WriteI, ReadI, ReadI]>;
[all …]
H A DAArch64SMEInstrInfo.td44 def AllocateZABuffer : Pseudo<(outs GPR64sp:$dst), (ins GPR64:$size), []>, Sched<[WriteI]> {}
52 …j : Pseudo<(outs), (ins GPR64:$buffer), [(AArch64InitTPIDR2Obj GPR64:$buffer)]>, Sched<[WriteI]> {}
H A DAArch64SchedNeoverseN2.td625 def : InstRW<[WriteI], (instrs COPY)>;
646 def : SchedAlias<WriteI, N2Write_1cyc_1I>;
861 def : InstRW<[N2Write_6cyc_1I_1L, WriteI], (instregex "^LDR[BHSDQ]post$")>;
H A DAArch64SchedExynosM3.td199 def : SchedAlias<WriteI, M3WriteA1>;
H A DAArch64SchedAmpere1.td587 def : WriteRes<WriteI, [Ampere1UnitAB]>; // ALU
H A DAArch64SchedAmpere1B.td543 def : WriteRes<WriteI, [Ampere1BUnitAB]>; // ALU
H A DAArch64SchedExynosM4.td510 def : SchedAlias<WriteI, M4WriteA1>;
H A DAArch64SchedExynosM5.td543 def : SchedAlias<WriteI, M5WriteA1W>;
H A DAArch64SchedNeoverseV2.td1089 def : InstRW<[WriteI], (instrs COPY)>;
1110 def : SchedAlias<WriteI, V2Write_1cyc_1I>;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveInterval.h944 LiveRange::iterator WriteI; variable

12