Searched refs:WriteCSR (Results 1 – 19 of 19) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSchedSyntacoreSCR1.td | 80 def : WriteRes<WriteCSR, []>;
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| H A D | RISCVSchedRocket.td | 182 def : WriteRes<WriteCSR, []>;
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| H A D | RISCVSchedMIPSP8700.td | 124 def : WriteRes<WriteCSR, [p8700ALQ]>;
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| H A D | RISCVSchedXiangShanNanHu.td | 204 def : WriteRes<WriteCSR, [XS2MISC]>;
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| H A D | RISCVSchedTTAscalonD8.td | 210 def : WriteRes<WriteCSR, [AscalonFXA]>;
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| H A D | RISCVSchedSiFiveP500.td | 242 def : WriteRes<WriteCSR, [SiFiveP500SYS]>;
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| H A D | RISCVSchedAndes45.td | 228 def : WriteRes<WriteCSR, [Andes45CSR]>;
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| H A D | RISCVSchedSyntacoreSCR7.td | 236 def : WriteRes<WriteCSR, []>;
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| H A D | RISCVSchedSpacemitX60.td | 236 def : WriteRes<WriteCSR, [SMX60_IEU]>;
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| H A D | RISCVSchedSyntacoreSCR345.td | 175 def : WriteRes<WriteCSR, []>;
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| H A D | RISCVSchedGenericOOO.td | 220 def : WriteRes<WriteCSR, [GenericOOOALU]>;
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| H A D | RISCVSchedule.td | 30 def WriteCSR : SchedWrite; // CSR instructions
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| H A D | RISCVSchedSiFiveP800.td | 853 def : WriteRes<WriteCSR, [SiFiveP800SYS]>;
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| H A D | RISCVSchedSiFiveP400.td | 910 def : WriteRes<WriteCSR, [SiFiveP400SYS]>;
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| H A D | RISCVInstrInfo.td | 683 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
690 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR]>;
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| H A D | RISCVSchedSiFiveP600.td | 1167 def : WriteRes<WriteCSR, [SiFiveP600SYS]>;
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| H A D | RISCVSchedSiFive7.td | 1009 def : WriteRes<WriteCSR, [PipeB]>;
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterContextDarwin_riscv32.h | 228 int WriteCSR();
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| H A D | RegisterContextDarwin_riscv32.cpp | 903 int RegisterContextDarwin_riscv32::WriteCSR() { in WriteCSR() function in RegisterContextDarwin_riscv32
941 return WriteCSR(); in WriteRegisterSet()
1214 if (WriteCSR() == 0) in WriteAllRegisterValues()
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