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Searched refs:WRITE_REG32 (Results 1 – 12 of 12) sorted by relevance

/freebsd/sys/dev/qlxge/
H A Dqls_hw.c263 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_unicast_mac_addr()
264 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower); in qls_config_unicast_mac_addr()
273 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_unicast_mac_addr()
274 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper); in qls_config_unicast_mac_addr()
283 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_unicast_mac_addr()
289 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, value); in qls_config_unicast_mac_addr()
328 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_mcast_mac_addr()
329 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower); in qls_config_mcast_mac_addr()
339 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_mcast_mac_addr()
340 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper); in qls_config_mcast_mac_addr()
[all …]
H A Dqls_dump.c404 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ); in qls_rd_mpi_reg()
428 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data); in qls_wr_mpi_reg()
430 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg); in qls_wr_mpi_reg()
609 WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \ in qls_rd_serdes_reg()
813 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ in qls_unpause_mpi_risc()
825 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ in qls_pause_mpi_risc()
849 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); in qls_get_intr_states()
865 WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R)); in qls_rd_xgmac_reg()
1218 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ in qls_get_probe()
1231 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ in qls_get_probe()
[all …]
H A Dqls_hw.h903 #define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) macro
910 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx))
917 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx))
H A Dqls_isr.c355 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_CLR_RTH_INTR); in qls_mbx_isr()
/freebsd/sys/dev/qlxgb/
H A Dqla_hw.h795 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\
799 WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val)
802 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\
807 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\
809 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\
816 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\
823 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\
H A Dqla_reg.h231 #define WRITE_REG32(ha, reg, val) \ macro
/freebsd/sys/dev/qlxgbe/
H A Dql_misc.c70 WRITE_REG32(ha, wnd_reg, addr); in ql_rdwr_indreg32()
87 WRITE_REG32(ha, Q8_WILD_CARD, *val); in ql_rdwr_indreg32()
1307 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0); in qla_ld_fw_init()
1315 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678); in qla_ld_fw_init()
1387 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0); in ql_start_sequence()
1395 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678); in ql_start_sequence()
H A Dql_inline.h64 WRITE_REG32(ha, id_reg, id_val); in qla_sem_lock()
H A Dql_isr.c765 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0); in ql_mbx_isr()
881 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); in ql_mbx_isr()
882 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); in ql_mbx_isr()
H A Dql_hw.h205 #define WRITE_REG32(ha, reg, val) \ macro
1719 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
H A Dql_hw.c1434 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox); in qla_mbx_cmd()
1438 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1); in qla_mbx_cmd()
1480 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); in qla_mbx_cmd()
1481 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); in qla_mbx_cmd()
2863 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2); in qla_confirm_9kb_enable()
2864 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); in qla_confirm_9kb_enable()
H A Dql_ioctl.c118 WRITE_REG32(ha, u.rv->reg, u.rv->val); in ql_eioctl()