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Searched refs:Vn (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2637 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2638 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2639 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2641 let TwoOperandAliasConstraint = "$Vn = $Vd";
2650 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2651 OpcodeStr, "$Vd, $Vn, $Vm", "",
2652 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2654 let TwoOperandAliasConstraint = "$Vn = $Vd";
2662 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2663 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
[all …]
H A DARMInstrCDE.td430 iname#"\t$coproc, $Vd, $Vn, $Vm, $imm", params.Cstr> {
444 bits<5> Vn;
447 let Inst{19-16} = Vn{4-1};
449 let Inst{7} = Vn{0};
460 bits<5> Vn;
463 let Inst{19-16} = Vn{3-0};
465 let Inst{7} = Vn{4};
475 let Rn = (ins regclass:$Vn);
H A DARMInstrFormats.td2477 bits<5> Vn;
2482 let Inst{19-16} = Vn{3-0};
2483 let Inst{7} = Vn{4};
2492 Dt, "$Vd, $Vn, $Vm", "", pattern> {
2494 bits<5> Vn;
2500 let Inst{19-16} = Vn{3-0};
2501 let Inst{7} = Vn{4};
2522 bits<5> Vn;
2528 let Inst{19-16} = Vn{3-0};
2529 let Inst{7} = Vn{4};
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td1763 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))),
1764 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>;
1766 def : Pat<(v2i64 (int_aarch64_crypto_sha512su0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
1767 (SHA512SU0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
1779 : Pat<(xor (xor (VecTy V128:$Vn), (VecTy V128:$Vm)), (VecTy V128:$Va)),
1780 (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
1788 : Pat<(xor (VecTy V128:$Vn), (and (VecTy V128:$Vm), (vnot (VecTy V128:$Va)))),
1789 (BCAX (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
1811 def : Pat<(v2i64 (int_aarch64_crypto_rax1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
1812 (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
[all …]
H A DAArch64InstrFormats.td7143 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
7144 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
7145 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
7146 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
7148 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
7149 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
7150 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
7151 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
7152 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
7153 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
[all …]
H A DAArch64InstrGISel.td405 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
H A DAArch64SchedCyclone.td336 // ORR.16b Vd,Vn,Vn
H A DSVEInstrFormats.td7828 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
7829 asm, "\t$Zd, $Pg/m, $Vn",
7833 bits<5> Vn;
7839 let Inst{9-5} = Vn;
7854 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
7855 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
7856 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
7857 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
7858 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
7859 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp6142 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); in DecodeNEONComplexLane64Instruction() local
6143 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); in DecodeNEONComplexLane64Instruction()
6157 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) in DecodeNEONComplexLane64Instruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td174 // bits<5> Vn : vector register input or output for operand n
178 // bits<5> Vn : vector index for address operand n