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Searched refs:Vm (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2525 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2526 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2531 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2532 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2540 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2541 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2547 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2548 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2554 : N2Vnp<op19_18, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2556 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
[all …]
H A DARMInstrCDE.td360 iname#"\t$coproc, $Vd, $Vm, $imm", params.Cstr> {
375 bits<5> Vm;
379 let Inst{3-0} = Vm{4-1};
380 let Inst{5} = Vm{0};
388 bits<5> Vm;
392 let Inst{3-0} = Vm{3-0};
393 let Inst{5} = Vm{4};
430 iname#"\t$coproc, $Vd, $Vn, $Vm, $imm", params.Cstr> {
443 bits<5> Vm;
450 let Inst{5} = Vm{0};
[all …]
H A DARMInstrFormats.td2370 bits<5> Vm;
2374 let Inst{3-0} = Vm{3-0};
2375 let Inst{5} = Vm{4};
2383 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
2385 bits<5> Vm;
2390 let Inst{5} = Vm{4};
2391 let Inst{3-0} = Vm{3-0};
2423 bits<5> Vm;
2427 let Inst{3-0} = Vm{3-0};
2428 let Inst{5} = Vm{4};
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td1763 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))),
1764 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>;
1766 def : Pat<(v2i64 (int_aarch64_crypto_sha512su0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
1767 (SHA512SU0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
1779 : Pat<(xor (xor (VecTy V128:$Vn), (VecTy V128:$Vm)), (VecTy V128:$Va)),
1780 (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
1788 : Pat<(xor (VecTy V128:$Vn), (and (VecTy V128:$Vm), (vnot (VecTy V128:$Va)))),
1789 (BCAX (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
1811 def : Pat<(v2i64 (int_aarch64_crypto_rax1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
1812 (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
[all …]
H A DAArch64InstrGISel.td405 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
H A DAArch64InstrFormats.td8499 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
8500 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
8504 bits<5> Vm;
8508 let Inst{20-16} = Vm;
8520 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
8521 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
8525 bits<5> Vm;
8529 let Inst{20-16} = Vm;
12097 bits<5> Vm;
12099 let Inst{20-16} = Vm;
[all …]
H A DSVEInstrFormats.td1824 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcOpType:$Vm),
1825 asm, "\t$Zdn, $Vm",
1828 bits<5> Vm;
1833 let Inst{9-5} = Vm;
1847 def : Pat<(nxv8f16 (op nxv8f16:$Zn, f16:$Vm)),
1848 (!cast<Instruction>(NAME # _H) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, hsub))>;
1849 def : Pat<(nxv4f32 (op nxv4f32:$Zn, f32:$Vm)),
1850 (!cast<Instruction>(NAME # _S) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, ssub))>;
1851 def : Pat<(nxv2f64 (op nxv2f64:$Zn, f64:$Vm)),
1852 (!cast<Instruction>(NAME # _D) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, dsub))>;
[all …]
/freebsd/secure/caroot/trusted/
H A DHiPKI_Root_CA_-_G1.pem116 /W3c1pzAtH2lsN0/Vm+h+fbkEkj9Bn8SV7apI09bA8PgcSojt/ewsTu8mL3WmKgM
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp6026 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTD() local
6027 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeVCVTD()
6070 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTD()
6085 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTQ() local
6086 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeVCVTQ()
6129 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTQ()
6144 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeNEONComplexLane64Instruction() local
6145 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeNEONComplexLane64Instruction()
6159 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeNEONComplexLane64Instruction()