Lines Matching refs:Vm
1689 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcOpType:$Vm),
1690 asm, "\t$Zdn, $Vm",
1693 bits<5> Vm;
1698 let Inst{9-5} = Vm;
1712 def : Pat<(nxv8f16 (op nxv8f16:$Zn, f16:$Vm)),
1713 (!cast<Instruction>(NAME # _H) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, hsub))>;
1714 def : Pat<(nxv4f32 (op nxv4f32:$Zn, f32:$Vm)),
1715 (!cast<Instruction>(NAME # _S) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, ssub))>;
1716 def : Pat<(nxv2f64 (op nxv2f64:$Zn, f64:$Vm)),
1717 (!cast<Instruction>(NAME # _D) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, dsub))>;
1719 def : Pat<(nxv8bf16 (op nxv8bf16:$Zn, bf16:$Vm)),
1720 (!cast<Instruction>(NAME # _H) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, hsub))>;
1723 def : Pat<(nxv16i8 (op (nxv16i8 ZPR:$Zn), (i32 (vector_extract (nxv16i8 ZPR:$Vm), 0)))),
1724 (!cast<Instruction>(NAME # _B) $Zn, ZPR:$Vm)>;
1725 def : Pat<(nxv8i16 (op (nxv8i16 ZPR:$Zn), (i32 (vector_extract (nxv8i16 ZPR:$Vm), 0)))),
1726 (!cast<Instruction>(NAME # _H) $Zn, ZPR:$Vm)>;
1727 def : Pat<(nxv4i32 (op (nxv4i32 ZPR:$Zn), (i32 (vector_extract (nxv4i32 ZPR:$Vm), 0)))),
1728 (!cast<Instruction>(NAME # _S) $Zn, ZPR: $Vm)>;
1729 def : Pat<(nxv2i64 (op (nxv2i64 ZPR:$Zn), (i64 (vector_extract (nxv2i64 ZPR:$Vm), 0)))),
1730 (!cast<Instruction>(NAME # _D) $Zn, ZPR:$Vm)>;