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Searched refs:VectorWidth (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DScalarizeMaskedMemIntrin.cpp108 static unsigned adjustForEndian(const DataLayout &DL, unsigned VectorWidth, in adjustForEndian() argument
110 return DL.isBigEndian() ? VectorWidth - 1 - Idx : Idx; in adjustForEndian()
178 unsigned VectorWidth = cast<FixedVectorType>(VecType)->getNumElements(); in scalarizeMaskedLoad() local
184 for (unsigned Idx = 0; Idx < VectorWidth; ++Idx) { in scalarizeMaskedLoad()
229 if (VectorWidth != 1 && !HasBranchDivergence) { in scalarizeMaskedLoad()
230 Type *SclrMaskTy = Builder.getIntNTy(VectorWidth); in scalarizeMaskedLoad()
234 for (unsigned Idx = 0; Idx < VectorWidth; ++Idx) { in scalarizeMaskedLoad()
247 VectorWidth, adjustForEndian(DL, VectorWidth, Idx))); in scalarizeMaskedLoad()
249 Builder.getIntN(VectorWidth, 0)); in scalarizeMaskedLoad()
348 unsigned VectorWidth = cast<FixedVectorType>(VecType)->getNumElements(); in scalarizeMaskedStore() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredication.cpp208 int VectorWidth = in IsSafeActiveMask() local
210 if (VectorWidth != 2 && VectorWidth != 4 && VectorWidth != 8 && in IsSafeActiveMask()
211 VectorWidth != 16) in IsSafeActiveMask()
248 if (VectorWidth != StepValue) { in IsSafeActiveMask()
250 << " doesn't match vector width " << VectorWidth << "\n"); in IsSafeActiveMask()
268 (ConstElemCount->getZExtValue() + VectorWidth - 1) / VectorWidth; in IsSafeActiveMask()
293 SE->getSCEV(ConstantInt::get(TripCount->getType(), VectorWidth)); in IsSafeActiveMask()
298 SE->getSCEV(ConstantInt::get(TripCount->getType(), VectorWidth - 1))); in IsSafeActiveMask()
311 dbgs() << "ARM TP: - VecWidth = " << VectorWidth << "\n"; in IsSafeActiveMask()
351 if (BaseC->getAPInt().urem(VectorWidth) == 0) in IsSafeActiveMask()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp607 int VectorWidth = VT.getSizeInBits(); in group2Shuffle() local
610 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle()
H A DX86MCInstLower.cpp1965 unsigned VectorWidth = in addConstantComments() local
1968 printConstant(C, VectorWidth, CS); in addConstantComments()
1986 unsigned VectorWidth = in addConstantComments() local
1989 printConstant(C, VectorWidth, CS); in addConstantComments()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DIRTranslator.cpp1601 unsigned VectorWidth = 0; in translateGetElementPtr() local
1607 VectorWidth = cast<FixedVectorType>(VT)->getNumElements(); in translateGetElementPtr()
1609 WantSplatVector = VectorWidth > 1; in translateGetElementPtr()
1616 .buildSplatBuildVector(LLT::fixed_vector(VectorWidth, PtrTy), in translateGetElementPtr()
1619 PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth); in translateGetElementPtr()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp3107 const SDLoc &DL, unsigned VectorWidth) { in extractSubVector() argument
3110 unsigned Factor = VT.getSizeInBits() / VectorWidth; in extractSubVector()
3115 unsigned ElemsPerChunk = VectorWidth / ElVT.getSizeInBits(); in extractSubVector()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp6333 if (unsigned VectorWidth = getContext().BuiltinInfo.getRequiredVectorWidth(BuiltinID)) in EmitBuiltinExpr() local
6334 LargestVectorWidth = std::max(LargestVectorWidth, VectorWidth); in EmitBuiltinExpr()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DAttr.td3479 let Args = [UnsignedArgument<"VectorWidth", /*opt*/1>];
3622 let Args = [UnsignedArgument<"VectorWidth">];