Home
last modified time | relevance | path

Searched refs:VecSize (Results 1 – 25 of 32) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.cpp479 unsigned VecSize = NumElts * ScalarBits; in DecodeVPERMILPMask() local
480 unsigned NumLanes = VecSize / 128; in DecodeVPERMILPMask()
482 assert((VecSize == 128 || VecSize == 256 || VecSize == 512) && in DecodeVPERMILPMask()
501 unsigned VecSize = NumElts * ScalarBits; in DecodeVPERMIL2PMask() local
502 unsigned NumLanes = VecSize / 128; in DecodeVPERMIL2PMask()
504 assert((VecSize == 128 || VecSize == 256) && "Unexpected vector size"); in DecodeVPERMIL2PMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction() local
171 SR == 0 ? 0 : VecSize/2); in runOnMachineFunction()
H A DHexagonPatternsHVX.td96 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
97 assert(isPowerOf2_32(VecSize));
98 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
100 int32_t L = Log2_32(VecSize);
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1397 SIInstrInfo::getIndirectGPRIDXPseudo(unsigned VecSize, in getIndirectGPRIDXPseudo() argument
1400 if (VecSize <= 32) // 4 bytes in getIndirectGPRIDXPseudo()
1402 if (VecSize <= 64) // 8 bytes in getIndirectGPRIDXPseudo()
1404 if (VecSize <= 96) // 12 bytes in getIndirectGPRIDXPseudo()
1406 if (VecSize <= 128) // 16 bytes in getIndirectGPRIDXPseudo()
1408 if (VecSize <= 160) // 20 bytes in getIndirectGPRIDXPseudo()
1410 if (VecSize <= 256) // 32 bytes in getIndirectGPRIDXPseudo()
1412 if (VecSize <= 288) // 36 bytes in getIndirectGPRIDXPseudo()
1414 if (VecSize <= 320) // 40 bytes in getIndirectGPRIDXPseudo()
1416 if (VecSize <= 352) // 44 bytes in getIndirectGPRIDXPseudo()
[all …]
H A DAMDGPUISelDAGToDAG.cpp3016 unsigned VecSize = Src.getValueSizeInBits(); in SelectVOP3PMods() local
3020 if (Lo.getValueSizeInBits() > VecSize) { in SelectVOP3PMods()
3022 (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In), in SelectVOP3PMods()
3023 MVT::getIntegerVT(VecSize), Lo); in SelectVOP3PMods()
3026 if (Hi.getValueSizeInBits() > VecSize) { in SelectVOP3PMods()
3028 (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In), in SelectVOP3PMods()
3029 MVT::getIntegerVT(VecSize), Hi); in SelectVOP3PMods()
3032 assert(Lo.getValueSizeInBits() <= VecSize && in SelectVOP3PMods()
3033 Hi.getValueSizeInBits() <= VecSize); in SelectVOP3PMods()
3039 if (VecSize == 32 || VecSize == Lo.getValueSizeInBits()) { in SelectVOP3PMods()
[all …]
H A DSIInstrInfo.h308 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
312 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
H A DSIISelLowering.cpp7204 unsigned VecSize = VecVT.getSizeInBits(); in lowerINSERT_VECTOR_ELT() local
7246 assert(VecSize <= 64 && "Expected target vector size to be <= 64 bits"); in lowerINSERT_VECTOR_ELT()
7248 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT()
7284 unsigned VecSize = VecVT.getSizeInBits(); in lowerEXTRACT_VECTOR_ELT() local
7296 if (VecSize == 128 || VecSize == 256 || VecSize == 512) { in lowerEXTRACT_VECTOR_ELT()
7301 if (VecSize == 128) { in lowerEXTRACT_VECTOR_ELT()
7309 } else if (VecSize == 256) { in lowerEXTRACT_VECTOR_ELT()
7322 assert(VecSize == 512); in lowerEXTRACT_VECTOR_ELT()
7348 assert(VecSize <= 64); in lowerEXTRACT_VECTOR_ELT()
7350 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerEXTRACT_VECTOR_ELT()
[all …]
H A DAMDGPURegisterBankInfo.cpp4291 unsigned VecSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); in getInstrMapping() local
4297 OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping()
4298 OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping()
H A DSIInstructions.td2399 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
2403 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset)
2409 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DHexagon.cpp148 uint64_t VecSize = T.hasFeature("hvx-length64b") ? 64*8 : 128*8; in classifyReturnType() local
149 if (Size == VecSize || Size == 2*VecSize) in classifyReturnType()
H A DARM.cpp729 unsigned VecSize = getContext().getTypeSize(VT); in isHomogeneousAggregateBaseType() local
730 if (VecSize == 64 || VecSize == 128) in isHomogeneousAggregateBaseType()
H A DAArch64.cpp514 unsigned VecSize = getContext().getTypeSize(VT); in isHomogeneousAggregateBaseType() local
515 if (VecSize == 64 || VecSize == 128) in isHomogeneousAggregateBaseType()
H A DX86.cpp67 unsigned VecSize = Context.getTypeSize(VT); in isX86VectorTypeForVectorCall() local
68 if (VecSize == 128 || VecSize == 256 || VecSize == 512) in isX86VectorTypeForVectorCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h437 VecSize = 3 << VecSizeShift, enumerator
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaType.cpp2321 std::optional<llvm::APSInt> VecSize = in BuildVectorType() local
2323 if (!VecSize) { in BuildVectorType()
2335 if (!VecSize->isIntN(61)) { in BuildVectorType()
2341 uint64_t VectorSizeBits = VecSize->getZExtValue() * 8; in BuildVectorType()
8248 unsigned VecSize = static_cast<unsigned>(SveVectorSizeInBits.getZExtValue()); in HandleArmSveVectorBitsTypeAttr() local
8251 if (VecSize != S.getLangOpts().VScaleMin * 128) { in HandleArmSveVectorBitsTypeAttr()
8253 << VecSize << S.getLangOpts().VScaleMin * 128; in HandleArmSveVectorBitsTypeAttr()
8273 VecSize /= S.Context.getCharWidth() * S.Context.getCharWidth(); in HandleArmSveVectorBitsTypeAttr()
8276 VecSize /= TypeSize; in HandleArmSveVectorBitsTypeAttr()
8277 CurType = S.Context.getVectorType(EltType, VecSize, VecKind); in HandleArmSveVectorBitsTypeAttr()
[all …]
H A DSemaExpr.cpp11379 const llvm::ElementCount VecSize = in checkSizelessVectorShift() local
11382 S.Context.getScalableVectorType(LHSEleType, VecSize.getKnownMinValue()); in checkSizelessVectorShift()
11394 const llvm::ElementCount VecSize = in checkSizelessVectorShift() local
11401 S.Context.getScalableVectorType(RHSEleType, VecSize.getKnownMinValue()); in checkSizelessVectorShift()
12578 const llvm::ElementCount VecSize = Context.getBuiltinVectorTypeInfo(VTy).EC; in GetSignedSizelessVectorType() local
12579 return Context.getScalableVectorType(IntTy, VecSize.getKnownMinValue()); in GetSignedSizelessVectorType()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp2055 unsigned VecSize; in tryLoadParam() local
2060 VecSize = 1; in tryLoadParam()
2063 VecSize = 2; in tryLoadParam()
2066 VecSize = 4; in tryLoadParam()
2075 switch (VecSize) { in tryLoadParam()
2102 if (VecSize == 1) { in tryLoadParam()
2104 } else if (VecSize == 2) { in tryLoadParam()
H A DNVPTXReplaceImageHandles.cpp1761 unsigned VecSize = in processInstr()
1765 MachineOperand &SurfHandle = MI.getOperand(VecSize); in processInstr()
1749 unsigned VecSize = processInstr() local
H A DNVPTXAsmPrinter.cpp179 unsigned VecSize = in lowerImageHandleOperand() local
183 if (OpNo == VecSize && MO.isImm()) { in lowerImageHandleOperand()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp1192 int VecSize = in isShuffleEquivalentToSelect() local
1196 if (MaskSize != VecSize) in isShuffleEquivalentToSelect()
1203 if (Elt != -1 && Elt != i && Elt != i + VecSize) in isShuffleEquivalentToSelect()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DConstants.cpp1334 unsigned VecSize = V.size(); in getTypeForElements() local
1335 SmallVector<Type*, 16> EltTypes(VecSize); in getTypeForElements()
1336 for (unsigned i = 0; i != VecSize; ++i) in getTypeForElements()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1920 size_t VecSize = Vec.size(); in SimplifyValuePattern() local
1921 if (VecSize == 1) in SimplifyValuePattern()
1923 if (!isPowerOf2_64(VecSize)) in SimplifyValuePattern()
1925 size_t HalfVecSize = VecSize / 2; in SimplifyValuePattern()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp109 return (Flags & ARMII::VecSize) >> ARMII::VecSizeShift; in getVecSize()
H A DARMInstrFormats.td426 bits<2> VecSize = 0;
447 let TSFlags{25-24} = VecSize;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6989 const unsigned VecSize = 16; in CC_AIX() local
6990 const Align VecAlign(VecSize); in CC_AIX()
7002 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
7028 for (unsigned I = 0; I != VecSize; I += PtrSize) in CC_AIX()
7030 State.AllocateStack(VecSize, VecAlign); in CC_AIX()
7034 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
7041 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
7050 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
7068 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
7071 for (unsigned I = 0; I != VecSize; I += PtrSize) { in CC_AIX()

12