| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | EarlyCSE.cpp | 1000 auto *Vec0 = dyn_cast<ConstantVector>(Mask0); in isNonTargetIntrinsicMatch() local
1002 if (!Vec0 || !Vec1) in isNonTargetIntrinsicMatch()
1004 if (Vec0->getType() != Vec1->getType()) in isNonTargetIntrinsicMatch()
1006 for (int i = 0, e = Vec0->getNumOperands(); i != e; ++i) { in isNonTargetIntrinsicMatch()
1007 Constant *Elem0 = Vec0->getOperand(i); in isNonTargetIntrinsicMatch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 2627 SDValue Vec0 = N->getOperand(0); in selectShuffle() local
2629 assert(Vec0.getValueType() == ResTy && Vec1.getValueType() == ResTy); in selectShuffle()
2635 if (!Vec0.isUndef()) { in selectShuffle()
2636 Results.push(TargetOpcode::COPY, ResTy, {Vec0}); in selectShuffle()
2653 Done = scalarizeShuffle(Mask, SDLoc(N), ResTy, Vec0, Vec1, N); in selectShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrMMA.td | 1081 dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0));
1095 Extracts.Vec0>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2073 SDValue Vec0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i8, in LowerBITCAST() local
2077 SDValue Extend0 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i16, Vec0); in LowerBITCAST()
5848 SDValue Vec0 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, AsInt); in ReplaceBITCAST() local
5854 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i8, {Vec0, Vec1})); in ReplaceBITCAST()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 1973 Register Vec0 = I.getOperand(2).getReg(); in selectIntegerDotExpansion() local
1976 SPIRVType *VecType = GR.getSPIRVTypeForVReg(Vec0); in selectIntegerDotExpansion()
1981 .addUse(Vec0) in selectIntegerDotExpansion()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15467 SDValue Vec0 = Op.getOperand(0); in LowerINSERT_SUBVECTOR() local
15482 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
15484 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
15497 if (isTypeLegal(InVT) && Vec0.isUndef()) in LowerINSERT_SUBVECTOR()
15512 Vec0 = getSVESafeBitCast(NarrowVT, Vec0, DAG); in LowerINSERT_SUBVECTOR()
15525 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
15531 SDValue LoVec0 = DAG.getNode(AArch64ISD::UUNPKLO, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
15541 if (Vec0.isUndef()) in LowerINSERT_SUBVECTOR()
15549 return DAG.getNode(ISD::VSELECT, DL, VT, PTrue, ScalableVec1, Vec0); in LowerINSERT_SUBVECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 12987 SDValue Vec0 = getBuildVector(VecVT, dl, Scalars0); in UnrollVectorOp() local
12989 return getMergeValues({Vec0, Vec1}, dl); in UnrollVectorOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 8036 SDValue Vec0 = SVN->getOperand(VecIdx0); in lowerVECTOR_SHUFFLE() local
8037 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec0, in lowerVECTOR_SHUFFLE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 51034 SDValue Vec0 = N0.getOperand(0); in combineBitOpWithMOVMSK() local
51036 EVT VecVT0 = Vec0.getValueType(); in combineBitOpWithMOVMSK()
51048 DAG.getNode(VecOpc, DL, VecVT0, Vec0, DAG.getBitcast(VecVT0, Vec1)); in combineBitOpWithMOVMSK()
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