Searched refs:Vec0 (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | EarlyCSE.cpp | 1011 auto *Vec0 = dyn_cast<ConstantVector>(Mask0); in isNonTargetIntrinsicMatch() local
1013 if (!Vec0 || !Vec1) in isNonTargetIntrinsicMatch()
1015 if (Vec0->getType() != Vec1->getType()) in isNonTargetIntrinsicMatch()
1017 for (int i = 0, e = Vec0->getNumOperands(); i != e; ++i) { in isNonTargetIntrinsicMatch()
1018 Constant *Elem0 = Vec0->getOperand(i); in isNonTargetIntrinsicMatch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 2636 SDValue Vec0 = N->getOperand(0); in selectShuffle()
2638 assert(Vec0.getValueType() == ResTy && Vec1.getValueType() == ResTy); in selectShuffle()
2644 if (!Vec0.isUndef()) { in selectShuffle()
2645 Results.push(TargetOpcode::COPY, ResTy, {Vec0}); in selectShuffle()
2662 Done = scalarizeShuffle(Mask, SDLoc(N), ResTy, Vec0, Vec1, N); in selectShuffle()
2639 SDValue Vec0 = N->getOperand(0); selectShuffle() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrMMA.td | 1076 dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0));
1090 Extracts.Vec0>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 14571 SDValue Vec0 = Op.getOperand(0); in LowerINSERT_SUBVECTOR() local
14586 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
14588 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
14612 Vec0 = getSVESafeBitCast(NarrowVT, Vec0, DAG); in LowerINSERT_SUBVECTOR()
14624 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
14629 SDValue LoVec0 = DAG.getNode(AArch64ISD::UUNPKLO, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
14638 if (Vec0.isUndef()) in LowerINSERT_SUBVECTOR()
14646 return DAG.getNode(ISD::VSELECT, DL, VT, PTrue, ScalableVec1, Vec0); in LowerINSERT_SUBVECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 12416 SDValue Vec0 = getBuildVector(VT, dl, Scalars0); in UnrollVectorOp() local
12418 return getMergeValues({Vec0, Vec1}, dl); in UnrollVectorOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 7422 SDValue Vec0 = SVN->getOperand(VecIdx0); in lowerVECTOR_SHUFFLE() local
7424 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 49280 SDValue Vec0 = N0.getOperand(0); in combineBitOpWithMOVMSK() local
49282 EVT VecVT0 = Vec0.getValueType(); in combineBitOpWithMOVMSK()
49295 DAG.getNode(VecOpc, DL, VecVT0, Vec0, DAG.getBitcast(VecVT0, Vec1)); in combineBitOpWithMOVMSK()
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