| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | Analysis.h | 66 SmallVectorImpl<EVT> &ValueVTs,
71 SmallVectorImpl<EVT> &ValueVTs,
78 Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
81 ComputeValueVTs(TLI, DL, Ty, ValueVTs, nullptr, Offsets, StartingOffset);
84 Type *Ty, SmallVectorImpl<EVT> &ValueVTs, in ComputeValueVTs() argument
87 ComputeValueVTs(TLI, DL, Ty, ValueVTs, nullptr, FixedOffsets, StartingOffset); in ComputeValueVTs()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 291 SmallVector<EVT, 4> ValueVTs; in set() local
292 ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs); in set()
293 for (EVT VT : ValueVTs) { in set()
383 SmallVector<EVT, 4> ValueVTs; in CreateRegs() local
384 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); in CreateRegs()
387 for (EVT ValueVT : ValueVTs) { in CreateRegs()
443 SmallVector<EVT, 1> ValueVTs; in ComputePHILiveOutRegInfo() local
444 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); in ComputePHILiveOutRegInfo()
445 assert(ValueVTs.size() == 1 && in ComputePHILiveOutRegInfo()
447 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo()
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| H A D | SelectionDAGBuilder.cpp | 850 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs), in RegsForValue()
856 ComputeValueVTs(TLI, DL, Ty, ValueVTs); in RegsForValue()
860 for (EVT ValueVT : ValueVTs) { in RegsForValue()
882 if (ValueVTs.empty()) in getCopyFromRegs()
888 SmallVector<SDValue, 4> Values(ValueVTs.size()); in getCopyFromRegs()
890 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { in getCopyFromRegs()
892 EVT ValueVT = ValueVTs[Value]; in getCopyFromRegs()
961 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); in getCopyFromRegs()
974 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { in getCopyToRegs()
1047 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && in AddInlineAsmOperands()
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| H A D | SelectionDAGBuilder.h | 728 SmallVector<EVT, 4> ValueVTs; member
763 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); in append()
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| H A D | LegalizeVectorOps.cpp | 1964 EVT ValueVTs[] = {TmpEltVT, MVT::Other}; in UnrollStrictFPOp() local
1989 SDValue ScalarOp = DAG.getNode(Node->getOpcode(), dl, ValueVTs, Opers); in UnrollStrictFPOp()
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| H A D | LegalizeIntegerTypes.cpp | 1753 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)}; in PromoteIntRes_UADDSUBO_CARRY() local
1756 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs), in PromoteIntRes_UADDSUBO_CARRY()
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| H A D | LegalizeVectorTypes.cpp | 306 EVT ValueVTs[] = {VT, MVT::Other}; in ScalarizeVecRes_StrictFPOp() local
331 SDValue Result = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(ValueVTs), in ScalarizeVecRes_StrictFPOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 45 Type *Ty, SmallVectorImpl<MVT> &ValueVTs) { in computeLegalValueVTs() argument
53 ValueVTs.push_back(RegisterVT); in computeLegalValueVTs()
58 Type *Ty, SmallVectorImpl<MVT> &ValueVTs) { in computeLegalValueVTs() argument
62 computeLegalValueVTs(TLI, F.getContext(), DL, Ty, ValueVTs); in computeLegalValueVTs()
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| H A D | WebAssemblyFrameLowering.cpp | 70 SmallVector<EVT, 4> ValueVTs; in getLocalForStackObject() local
74 ComputeValueVTs(TLI, MF.getDataLayout(), AI->getAllocatedType(), ValueVTs); in getLocalForStackObject()
81 for (EVT ValueVT : ValueVTs) in getLocalForStackObject()
85 MFI.setObjectSize(FrameIndex, ValueVTs.size()); in getLocalForStackObject()
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| H A D | WebAssemblyMachineFunctionInfo.h | 160 SmallVectorImpl<MVT> &ValueVTs);
163 SmallVectorImpl<MVT> &ValueVTs);
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 80 Type *Ty, SmallVectorImpl<EVT> &ValueVTs, in ComputeValueVTs() argument
100 ComputeValueVTs(TLI, DL, *EI, ValueVTs, MemVTs, Offsets, in ComputeValueVTs()
110 ComputeValueVTs(TLI, DL, EltTy, ValueVTs, MemVTs, Offsets, in ComputeValueVTs()
118 ValueVTs.push_back(TLI.getValueType(DL, Ty)); in ComputeValueVTs()
126 Type *Ty, SmallVectorImpl<EVT> &ValueVTs, in ComputeValueVTs() argument
133 ComputeValueVTs(TLI, DL, Ty, ValueVTs, MemVTs, &Offsets, Offset); in ComputeValueVTs()
137 ComputeValueVTs(TLI, DL, Ty, ValueVTs, MemVTs, nullptr, Offset); in ComputeValueVTs()
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| H A D | TargetLoweringBase.cpp | 1642 SmallVector<EVT, 4> ValueVTs; in GetReturnInfo() local
1643 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); in GetReturnInfo()
1644 unsigned NumValues = ValueVTs.size(); in GetReturnInfo()
1648 EVT VT = ValueVTs[j]; in GetReturnInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 1060 SmallVector<EVT, 1> ValueVTs; in insertSRetIncomingArgument() local
1061 ComputeValueVTs(*TLI, DL, PtrTy, ValueVTs); in insertSRetIncomingArgument()
1064 assert(ValueVTs.size() == 1); in insertSRetIncomingArgument()
1066 ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(PtrTy->getContext()), in insertSRetIncomingArgument()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 1216 SmallVector<EVT, 4> ValueVTs; in adjustInliningThresholdUsingCallee() local
1217 ComputeValueVTs(*TLI, DL, A.get()->getType(), ValueVTs); in adjustInliningThresholdUsingCallee()
1218 for (auto ArgVT : ValueVTs) { in adjustInliningThresholdUsingCallee()
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| H A D | AMDGPUISelLowering.cpp | 1181 SmallVector<EVT, 16> ValueVTs; in analyzeFormalArgumentsCompute() local
1183 ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset); in analyzeFormalArgumentsCompute()
1185 for (unsigned Value = 0, NumValues = ValueVTs.size(); in analyzeFormalArgumentsCompute()
1189 EVT ArgVT = ValueVTs[Value]; in analyzeFormalArgumentsCompute()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 169 Type *Ty, SmallVectorImpl<EVT> &ValueVTs, in ComputePTXValueVTs() argument
177 ValueVTs.push_back(EVT(MVT::i64)); in ComputePTXValueVTs()
178 ValueVTs.push_back(EVT(MVT::i64)); in ComputePTXValueVTs()
193 ComputePTXValueVTs(TLI, DL, EI, ValueVTs, Offsets, in ComputePTXValueVTs()
234 ValueVTs.push_back(EltVT); in ComputePTXValueVTs()
239 ValueVTs.push_back(VT); in ComputePTXValueVTs()
291 unsigned Idx, uint32_t AccessSize, const SmallVectorImpl<EVT> &ValueVTs, in CanMergeParamLoadStoresStartingAt() argument
301 EVT EltVT = ValueVTs[Idx]; in CanMergeParamLoadStoresStartingAt()
314 if (Idx + NumElts > ValueVTs.size()) in CanMergeParamLoadStoresStartingAt()
323 if (ValueVTs[j] != EltVT) in CanMergeParamLoadStoresStartingAt()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 22117 SmallVector<EVT, 4> ValueVTs; in constructArgInfos() local
22118 ComputeValueVTs(*TLI, DL, Ty, ValueVTs); in constructArgInfos()
22120 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues; in constructArgInfos()
22122 EVT VT = ValueVTs[Value]; in constructArgInfos()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 26736 SmallVector<EVT> ValueVTs; in functionArgumentNeedsConsecutiveRegisters() local
26737 ComputeValueVTs(*this, DL, Ty, ValueVTs); in functionArgumentNeedsConsecutiveRegisters()
26738 return all_equal(ValueVTs); in functionArgumentNeedsConsecutiveRegisters()
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