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Searched refs:ValReg (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp78 unsigned ValReg; in EmitTargetCodeForMemset() local
85 ValReg = X86::EAX; in EmitTargetCodeForMemset()
90 ValReg = X86::RAX; in EmitTargetCodeForMemset()
96 ValReg = X86::AX; in EmitTargetCodeForMemset()
101 ValReg = X86::AL; in EmitTargetCodeForMemset()
111 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
H A DX86FastISel.cpp83 bool X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM,
479 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM, in X86FastEmitStore() argument
499 .addReg(ValReg).addImm(1); in X86FastEmitStore()
500 ValReg = AndResult; in X86FastEmitStore()
642 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
645 addFullAddress(MIB, AM).addReg(ValReg); in X86FastEmitStore()
689 Register ValReg = getRegForValue(Val); in X86FastEmitStore() local
690 if (ValReg == 0) in X86FastEmitStore()
693 return X86FastEmitStore(VT, ValReg, AM, MMO, Aligned); in X86FastEmitStore()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h143 std::optional<ValueAndVReg> &ValReg; member
144 GCstAndRegMatch(std::optional<ValueAndVReg> &ValReg) : ValReg(ValReg) {} in GCstAndRegMatch()
146 ValReg = getIConstantVRegValWithLookThrough(Reg, MRI); in match()
147 return ValReg ? true : false; in match()
151 inline GCstAndRegMatch m_GCst(std::optional<ValueAndVReg> &ValReg) { in m_GCst() argument
152 return GCstAndRegMatch(ValReg); in m_GCst()
H A DCallLowering.h325 Register extendRegister(Register ValReg, const CCValAssign &VA,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1292 Register CallLowering::ValueHandler::extendRegister(Register ValReg, in extendRegister() argument
1299 return ValReg; in extendRegister()
1303 return ValReg; in extendRegister()
1307 const LLT ValRegTy = MRI.getType(ValReg); in extendRegister()
1312 ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0); in extendRegister()
1322 return ValReg; in extendRegister()
1324 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
1329 MIRBuilder.buildSExt(NewReg, ValReg); in extendRegister()
1334 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
H A DLegalizerHelper.cpp4624 Register ValReg = LdStMI.getReg(0); in reduceLoadStoreWidth() local
4626 LLT ValTy = MRI.getType(ValReg); in reduceLoadStoreWidth()
4641 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, in reduceLoadStoreWidth()
4698 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, in reduceLoadStoreWidth()
8254 Register ValReg = MI.getOperand(ValRegIndex).getReg(); in lowerReadWriteRegister() local
8255 const LLT Ty = MRI.getType(ValReg); in lowerReadWriteRegister()
8264 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
8266 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp339 MachineBasicBlock *MBB, Register ValReg, in expandAtomicBinOp()
341 BuildMI(MBB, DL, TII->get(LoongArch::SLL_W), ValReg) in expandAtomicBinOp()
342 .addReg(ValReg) in expandAtomicBinOp()
344 BuildMI(MBB, DL, TII->get(LoongArch::SRA_W), ValReg) in expandAtomicBinOp()
345 .addReg(ValReg) in expandAtomicBinOp()
351 insertSext(const LoongArchInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register ValReg,Register ShamtReg) insertSext() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp428 MachineBasicBlock *MBB, Register ValReg, in expandAtomicMinMaxOp()
430 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in expandAtomicMinMaxOp()
431 .addReg(ValReg) in expandAtomicMinMaxOp()
433 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in expandAtomicMinMaxOp()
434 .addReg(ValReg) in expandAtomicMinMaxOp()
399 insertSext(const RISCVInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register ValReg,Register ShamtReg) insertSext() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp2039 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
2043 .addReg(ValReg) in emitInstruction()
2050 .addReg(ValReg) in emitInstruction()
2053 .addReg(ValReg) in emitInstruction()
2060 .addReg(ValReg) in emitInstruction()
2105 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
2109 .addReg(ValReg) in emitInstruction()
2119 .addReg(ValReg) in emitInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1744 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoadStore() local
1745 const LLT ValTy = MRI.getType(ValReg); in legalizeLoadStore()
1775 ValReg, {NewI->getOperand(0), NewI->getOperand(1)}); in legalizeLoadStore()
1812 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
1816 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
H A DAArch64InstructionSelector.cpp2909 Register ValReg = LdSt.getReg(0); in select() local
2910 if (MRI.getType(ValReg).getSizeInBits() == 64 && MemSizeInBits != 64) { in select()
2933 const Register ValReg = LdSt.getReg(0); in select() local
2934 const LLT ValTy = MRI.getType(ValReg); in select()
2935 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
2948 .addReg(ValReg, 0, SubReg) in select()
6562 Register ValReg = I.getOperand(2).getReg(); in selectIntrinsic() local
6578 MIB.buildCopy({AArch64::X16}, {ValReg}); in selectIntrinsic()
6596 Register ValReg = I.getOperand(2).getReg(); in selectIntrinsic() local
6605 MIB.buildCopy({AArch64::X16}, {ValReg}); in selectIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp1603 Register ValReg = MI.getOperand(3).getReg(); in selectDSOrderedIntrinsic() local
1606 .addReg(ValReg) in selectDSOrderedIntrinsic()
3116 Register ValReg = MI.getOperand(2).getReg(); in selectG_INSERT_VECTOR_ELT() local
3120 LLT ValTy = MRI->getType(ValReg); in selectG_INSERT_VECTOR_ELT()
3125 const RegisterBank *ValRB = RBI.getRegBank(ValReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
3142 !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
3167 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
3177 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
H A DAMDGPULegalizerInfo.cpp3086 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoad() local
3087 LLT ValTy = MRI.getType(ValReg); in legalizeLoad()
3129 B.buildTrunc(ValReg, WideLoad).getReg(0); in legalizeLoad()
3137 B.buildExtract(ValReg, WideLoad, 0); in legalizeLoad()
3142 B.buildDeleteTrailingVectorElements(ValReg, WideLoad); in legalizeLoad()