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Searched refs:ValReg (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h152 std::optional<ValueAndVReg> &ValReg; member
153 GCstAndRegMatch(std::optional<ValueAndVReg> &ValReg) : ValReg(ValReg) {} in GCstAndRegMatch()
155 ValReg = getIConstantVRegValWithLookThrough(Reg, MRI); in match()
156 return ValReg ? true : false; in match()
160 inline GCstAndRegMatch m_GCst(std::optional<ValueAndVReg> &ValReg) { in m_GCst() argument
161 return GCstAndRegMatch(ValReg); in m_GCst()
H A DCallLowering.h326 Register extendRegister(Register ValReg, const CCValAssign &VA,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1291 Register CallLowering::ValueHandler::extendRegister(Register ValReg, in extendRegister() argument
1298 return ValReg; in extendRegister()
1302 return ValReg; in extendRegister()
1306 const LLT ValRegTy = MRI.getType(ValReg); in extendRegister()
1311 ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0); in extendRegister()
1321 return ValReg; in extendRegister()
1323 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
1328 MIRBuilder.buildSExt(NewReg, ValReg); in extendRegister()
1333 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
H A DLegalizerHelper.cpp5305 Register ValReg = LdStMI.getReg(0); in reduceLoadStoreWidth() local
5307 LLT ValTy = MRI.getType(ValReg); in reduceLoadStoreWidth()
5322 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, in reduceLoadStoreWidth()
5379 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, in reduceLoadStoreWidth()
9190 Register ValReg = MI.getOperand(ValRegIndex).getReg(); in lowerReadWriteRegister() local
9191 const LLT Ty = MRI.getType(ValReg); in lowerReadWriteRegister()
9203 MIRBuilder.buildUndef(ValReg); in lowerReadWriteRegister()
9210 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
9212 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp426 MachineBasicBlock *MBB, Register ValReg, in insertSext() argument
428 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
429 .addReg(ValReg) in insertSext()
431 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
432 .addReg(ValReg) in insertSext()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp357 MachineBasicBlock *MBB, Register ValReg, in insertSext() argument
359 BuildMI(MBB, DL, TII->get(LoongArch::SLL_W), ValReg) in insertSext()
360 .addReg(ValReg) in insertSext()
362 BuildMI(MBB, DL, TII->get(LoongArch::SRA_W), ValReg) in insertSext()
363 .addReg(ValReg) in insertSext()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp2073 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
2077 .addReg(ValReg) in emitInstruction()
2084 .addReg(ValReg) in emitInstruction()
2087 .addReg(ValReg) in emitInstruction()
2094 .addReg(ValReg) in emitInstruction()
2139 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
2143 .addReg(ValReg) in emitInstruction()
2153 .addReg(ValReg) in emitInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp83 bool X86FastEmitStore(EVT VT, Register ValReg, X86AddressMode &AM,
480 bool X86FastISel::X86FastEmitStore(EVT VT, Register ValReg, X86AddressMode &AM, in X86FastEmitStore() argument
500 .addReg(ValReg).addImm(1); in X86FastEmitStore()
501 ValReg = AndResult; in X86FastEmitStore()
643 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
646 addFullAddress(MIB, AM).addReg(ValReg); in X86FastEmitStore()
690 Register ValReg = getRegForValue(Val); in X86FastEmitStore() local
691 if (!ValReg) in X86FastEmitStore()
694 return X86FastEmitStore(VT, ValReg, AM, MMO, Aligned); in X86FastEmitStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1885 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoadStore() local
1886 const LLT ValTy = MRI.getType(ValReg); in legalizeLoadStore()
1916 ValReg, {NewI->getOperand(0), NewI->getOperand(1)}); in legalizeLoadStore()
1953 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
1957 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
H A DAArch64InstructionSelector.cpp3043 Register ValReg = LdSt.getReg(0); in select() local
3044 if (MRI.getType(ValReg).getSizeInBits() == 64 && MemSizeInBits != 64) { in select()
3067 const Register ValReg = LdSt.getReg(0); in select() local
3068 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
3069 LLT ValTy = MRI.getType(ValReg); in select()
3082 .addReg(ValReg, 0, SubReg) in select()
6722 Register ValReg = I.getOperand(2).getReg(); in selectIntrinsic() local
6738 MIB.buildCopy({AArch64::X16}, {ValReg}); in selectIntrinsic()
6756 Register ValReg = I.getOperand(2).getReg(); in selectIntrinsic() local
6766 MIB.buildCopy({AArch64::X16}, {ValReg}); in selectIntrinsic()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp1818 Register ValReg = MI.getOperand(3).getReg(); in selectDSOrderedIntrinsic() local
1821 .addReg(ValReg) in selectDSOrderedIntrinsic()
3310 Register ValReg = MI.getOperand(2).getReg(); in selectG_INSERT_VECTOR_ELT() local
3314 LLT ValTy = MRI->getType(ValReg); in selectG_INSERT_VECTOR_ELT()
3319 const RegisterBank *ValRB = RBI.getRegBank(ValReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
3336 !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
3361 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
3371 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
H A DAMDGPULegalizerInfo.cpp3144 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoad() local
3145 LLT ValTy = MRI.getType(ValReg); in legalizeLoad()
3187 B.buildTrunc(ValReg, WideLoad).getReg(0); in legalizeLoad()
3195 B.buildExtract(ValReg, WideLoad, 0); in legalizeLoad()
3200 B.buildDeleteTrailingVectorElements(ValReg, WideLoad); in legalizeLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp3706 Register ValReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); in selectFirstBitSet64() local
3707 if (!selectOpWithSrcs(ValReg, ResType, I, in selectFirstBitSet64()
3711 return selectOpWithSrcs(ResVReg, ResType, I, {ValReg, TmpReg}, AddOp); in selectFirstBitSet64()