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Searched refs:VTs (Results 1 – 25 of 54) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h81 const EVT *VTs; member
1203 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1204 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1208 assert(NumValues == VTs.NumVTs &&
1383 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1385 : SDNode(ISD::ADDRSPACECAST, Order, dl, VTs), SrcAddrSpace(SrcAS),
1408 SDVTList VTs, EVT memvt, MachineMemOperand *MMO);
1659 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1660 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1688 ShuffleVectorSDNode(SDVTList VTs, unsigned Order, const DebugLoc &dl,
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H A DSelectionDAG.h109 const EVT *VTs;
117 FastID(ID), VTs(VT), NumVTs(Num) {
122 SDVTList result = {VTs, NumVTs};
440 SDVTList VTs, EVT MemoryVT,
442 return SDNodeTy(Opc, Order, DebugLoc(), VTs, MemoryVT, MMO)
676 LLVM_ABI SDVTList getVTList(ArrayRef<EVT> VTs);
828 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
830 return getNode(ISD::CopyToReg, dl, VTs,
837 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
839 return getNode(ISD::CopyToReg, dl, VTs,
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp37 SDVTList VTs = Op == SystemZISD::CLC ? DAG.getVTList(MVT::i32, MVT::Other) in createMemMemNode() local
44 return DAG.getNode(Op, DL, VTs, Ops); in createMemMemNode()
203 SDVTList VTs = DAG.getVTList(PtrVT, MVT::i32, MVT::Other); in EmitTargetCodeForMemchr() local
209 SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain, in EmitTargetCodeForMemchr()
228 SDVTList VTs = DAG.getVTList(Dest.getValueType(), MVT::Other); in EmitTargetCodeForStrcpy() local
229 SDValue EndDest = DAG.getNode(SystemZISD::STPCPY, DL, VTs, Chain, Dest, Src, in EmitTargetCodeForStrcpy()
238 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::i32, MVT::Other); in EmitTargetCodeForStrcmp() local
240 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1, in EmitTargetCodeForStrcmp()
257 SDVTList VTs = DAG.getVTList(PtrVT, MVT::i32, MVT::Other); in getBoundedStrlen() local
258 SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain, in getBoundedStrlen()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp89 static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) { in makeVTList() argument
90 SDVTList Res = {VTs, NumVTs}; in makeVTList()
714 ID.AddPointer(VTList.VTs); in AddNodeIDValueTypes()
1765 SDVTList VTs = getVTList(EltVT); in getConstant() local
1767 AddNodeIDNode(ID, Opc, VTs, {}); in getConstant()
1777 N = newSDNode<ConstantSDNode>(isT, isO, Elt, VTs); in getConstant()
1845 SDVTList VTs = getVTList(EltVT); in getConstantFP() local
1847 AddNodeIDNode(ID, Opc, VTs, {}); in getConstantFP()
1856 N = newSDNode<ConstantFPSDNode>(isTarget, Elt, VTs); in getConstantFP()
1903 SDVTList VTs = getVTList(VT); in getGlobalAddress() local
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H A DSelectionDAGISel.cpp2445 const EVT VTs[] = {MVT::Other, MVT::Glue}; in Select_INLINEASM() local
2446 SDValue New = CurDAG->getNode(N->getOpcode(), DL, VTs, Ops); in Select_INLINEASM()
4128 SmallVector<EVT, 4> VTs; in SelectCodeCommon() local
4133 VTs.push_back(VT); in SelectCodeCommon()
4137 VTs.push_back(MVT::Other); in SelectCodeCommon()
4139 VTs.push_back(MVT::Glue); in SelectCodeCommon()
4144 if (VTs.size() == 1) in SelectCodeCommon()
4145 VTList = CurDAG->getVTList(VTs[0]); in SelectCodeCommon()
4146 else if (VTs.size() == 2) in SelectCodeCommon()
4147 VTList = CurDAG->getVTList(VTs[0], VTs[1]); in SelectCodeCommon()
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H A DScheduleDAGSDNodes.cpp144 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs, in CloneNodeWithValues() argument
150 SDVTList VTList = DAG->getVTList(VTs); in CloneNodeWithValues()
179 SmallVector<EVT, 4> VTs(N->values()); in AddGlue() local
181 VTs.push_back(MVT::Glue); in AddGlue()
183 CloneNodeWithValues(N, DAG, VTs, Glue); in AddGlue()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp70 ArrayRef<MVT> VTs) { in wasmSymbolSetType() argument
87 } else if (VTs.size() == 1) { in wasmSymbolSetType()
88 ValTy = WebAssembly::toValType(VTs[0]); in wasmSymbolSetType()
H A DWebAssemblyTypeUtilities.h63 ArrayRef<MVT> VTs);
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFSelectionDAGInfo.cpp34 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); in EmitTargetCodeForMemcpy() local
36 Dst = DAG.getNode(BPFISD::MEMCPY, dl, VTs, Chain, Dst, Src, in EmitTargetCodeForMemcpy()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp45 SmallVector<EVT, 4> VTs; in computeLegalValueVTs() local
46 ComputeValueVTs(TLI, DL, Ty, VTs); in computeLegalValueVTs()
48 for (EVT VT : VTs) { in computeLegalValueVTs()
H A DWebAssemblyMCInstLower.cpp60 SmallVector<MVT, 1> VTs; in GetGlobalAddressSymbol() local
61 computeLegalValueVTs(CurrentFunc, TM, GlobalVT, VTs); in GetGlobalAddressSymbol()
63 WebAssembly::wasmSymbolSetType(WasmSym, GlobalVT, VTs); in GetGlobalAddressSymbol()
H A DWebAssemblyAsmPrinter.cpp193 SmallVector<MVT, 1> VTs; in emitGlobalVariable() local
203 GV->getDataLayout(), GlobalVT, VTs); in emitGlobalVariable()
205 WebAssembly::wasmSymbolSetType(Sym, GlobalVT, VTs); in emitGlobalVariable()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.h358 SmallVector<ValueTypeByHwMode, 4> VTs; variable
386 ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; } in getValueTypes()
387 unsigned getNumValueTypes() const { return VTs.size(); } in getNumValueTypes()
391 if (VTNum < VTs.size()) in getValueTypeNum()
392 return VTs[VTNum]; in getValueTypeNum()
H A DDAGISelMatcher.cpp289 for (MVT::SimpleValueType VT : VTs) in printImpl()
312 return &M->CGI == &CGI && M->VTs == VTs && M->Operands == Operands && in isEqualImpl()
H A DDAGISelMatcher.h1030 const SmallVector<MVT::SimpleValueType, 3> VTs; variable
1045 : Matcher(isMorphNodeTo ? MorphNodeTo : EmitNode), CGI(cgi), VTs(vts), in EmitNodeMatcherCommon()
1052 unsigned getNumVTs() const { return VTs.size(); } in getNumVTs()
1054 assert(i < VTs.size()); in getVT()
1055 return VTs[i]; in getVT()
1064 const SmallVectorImpl<MVT::SimpleValueType> &getVTList() const { return VTs; } in getVTList()
H A DCodeGenRegisters.cpp695 VTs.push_back(getValueTypeByHwMode(Type, RegBank.getHwModes())); in CodeGenRegisterClass()
736 assert((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) && in CodeGenRegisterClass()
741 Size ? Size : VTs[0].getSimple().getSizeInBits(); in CodeGenRegisterClass()
797 VTs = Super.VTs; in inheritProperties()
816 if (llvm::is_contained(VTs, VT)) in hasType()
827 for (const ValueTypeByHwMode &OurVT : VTs) { in hasType()
2581 if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy)) in getSuperRegForSubReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp498 SDVTList VTs = CurDAG->getVTList(MVT::i32, MVT::i32); in getSBBZero() local
500 SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, VTs, {}), 0); in getSBBZero()
523 VTs = CurDAG->getVTList(SBBVT, MVT::i32); in getSBBZero()
525 CurDAG->getMachineNode(Opc, dl, VTs, in getSBBZero()
1075 SDVTList VTs = CurDAG->getVTList(NarrowVT, MVT::Other); in PreprocessISelDAG() local
1078 X86ISD::VBROADCAST_LOAD, dl, VTs, Ops, MemNode->getMemoryVT(), in PreprocessISelDAG()
1495 SDVTList VTs = CurDAG->getVTList(MVT::Other); in PreprocessISelDAG() local
1497 Store = CurDAG->getMemIntrinsicNode(X86ISD::FST, dl, VTs, Ops, MemVT, in PreprocessISelDAG()
1512 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other); in PreprocessISelDAG() local
1515 X86ISD::FLD, dl, VTs, Ops, MemVT, MPI, in PreprocessISelDAG()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCallingConvEmitter.cpp206 const ListInit *VTs = Action->getValueAsListInit("VTs"); in emitAction() local
207 for (unsigned I = 0, E = VTs->size(); I != E; ++I) { in emitAction()
208 const Record *VT = VTs->getElementAsRecord(I); in emitAction()
H A DRegisterInfoEmitter.cpp1264 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1327 std::vector<MVT::SimpleValueType> VTs; in runTargetDesc() local
1328 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1330 VTs.push_back(VVT.get(M).SimpleTy); in runTargetDesc()
1331 OS << ", /*VTLists+*/" << VTSeqs.get(VTs) << " }, // " in runTargetDesc()
H A DDAGISelMatcherOpt.cpp285 ArrayRef<MVT::SimpleValueType> VTs = EN->getVTList(); in ContractNodes() local
288 EN->getInstruction(), VTs, Operands, EN->hasChain(), in ContractNodes()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1610 SDVTList VTs; in lowerOverflowArithmetic() local
1612 VTs = DAG.getVTList(VT); in lowerOverflowArithmetic()
1615 VTs = DAG.getVTList(VT, MVT::i8); in lowerOverflowArithmetic()
1617 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerOverflowArithmetic()
2076 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i8); in EmitTest() local
2079 SDValue New = DAG.getNode(Opcode, DL, VTs, Ops); in EmitTest()
2125 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i8); in EmitCmp() local
2126 SDValue Sub = DAG.getNode(M68kISD::SUB, DL, VTs, Op0, Op1); in EmitCmp()
2226 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); in LowerSETCCCARRY() local
2228 DAG.getNode(M68kISD::SUBX, DL, VTs, LHS, RHS, Carry.getValue(1)); in LowerSETCCCARRY()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp229 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other, MVT::Glue); in EmitTargetCodeForMemcpy() local
237 Dst = DAG.getNode(ARMISD::MEMCPY, dl, VTs, Chain, Dst, Src, in EmitTargetCodeForMemcpy()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1546 SmallVector<EVT, 16> VTs; in LowerCall() local
1552 ComputePTXValueVTs(*this, DL, ETy, VTs, &Offsets, IsByVal ? 0 : VAOffset); in LowerCall()
1553 assert(VTs.size() == Offsets.size() && "Size mismatch"); in LowerCall()
1554 assert((IsByVal || VTs.size() == ArgOuts.size()) && "Size mismatch"); in LowerCall()
1641 assert(VTs.size() == 1 && "Scalar can't have multiple parts."); in LowerCall()
1654 VectorizePTXValueVTs(VTs, Offsets, ArgAlign, IsVAArg); in LowerCall()
1659 EVT EltVT = promoteScalarIntegerPTX(VTs[J]); in LowerCall()
1840 SmallVector<EVT, 16> VTs; in LowerCall() local
1842 ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets, 0); in LowerCall()
1843 assert(VTs.size() == Ins.size() && "Bad value decomposition"); in LowerCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp2906 SDVTList VTs = CurDAG->getVTList(MVT::Other); in SelectV65GatherPred() local
2909 SDNode *Result = CurDAG->getMachineNode(Opcode, dl, VTs, Ops); in SelectV65GatherPred()
2945 SDVTList VTs = CurDAG->getVTList(MVT::Other); in SelectV65Gather() local
2947 SDNode *Result = CurDAG->getMachineNode(Opcode, dl, VTs, Ops); in SelectV65Gather()
2962 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v64i1); in SelectHVXDualOutput() local
2963 Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops); in SelectHVXDualOutput()
2969 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v128i1); in SelectHVXDualOutput() local
2970 Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops); in SelectHVXDualOutput()
2976 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v64i1); in SelectHVXDualOutput() local
2977 Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Ops); in SelectHVXDualOutput()
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H A DHexagonISelLowering.cpp800 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other); in LowerREADCYCLECOUNTER() local
801 return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain); in LowerREADCYCLECOUNTER()
812 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other); in LowerREADSTEADYCOUNTER() local
813 return DAG.getNode(HexagonISD::READTIMER, dl, VTs, Chain); in LowerREADSTEADYCOUNTER()
854 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); in LowerDYNAMIC_STACKALLOC() local
855 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC); in LowerDYNAMIC_STACKALLOC()
3287 SDVTList VTs = Op.getNode()->getVTList(); in LowerUAddSubO() local
3288 assert(VTs.NumVTs == 2); in LowerUAddSubO()
3289 assert(VTs.VTs[1] == MVT::i1); in LowerUAddSubO()
3300 SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y}); in LowerUAddSubO()
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