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Searched refs:VSHL (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h738 X86_INTRINSIC_DATA(avx2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0),
739 X86_INTRINSIC_DATA(avx2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0),
740 X86_INTRINSIC_DATA(avx2_psll_w, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1295 X86_INTRINSIC_DATA(avx512_psll_d_512, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1296 X86_INTRINSIC_DATA(avx512_psll_q_512, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1297 X86_INTRINSIC_DATA(avx512_psll_w_512, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1973 X86_INTRINSIC_DATA(sse2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1974 X86_INTRINSIC_DATA(sse2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1975 X86_INTRINSIC_DATA(sse2_psll_w, INTR_TYPE_2OP, X86ISD::VSHL, 0),
H A DX86ISelLowering.h376 VSHL, enumerator
H A DX86InstrFragmentsSIMD.td253 def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>;
H A DX86ISelLowering.cpp26009 case X86ISD::VSHL: in getTargetVShiftUniformOpcode()
26011 return IsVariable ? X86ISD::VSHL : X86ISD::VSHLI; in getTargetVShiftUniformOpcode()
35069 NODE_NAME_CASE(VSHL) in getTargetNodeName()
42463 if (N0.getOpcode() == X86ISD::VSHL || N0.getOpcode() == X86ISD::VSHLI || in combineTargetShuffle()
42786 case X86ISD::VSHL: in combineTargetShuffle()
43546 case X86ISD::VSHL: in SimplifyDemandedVectorEltsForTargetNode()
43558 return (UseOpc == X86ISD::VSHL || UseOpc == X86ISD::VSRL || in SimplifyDemandedVectorEltsForTargetNode()
44060 case X86ISD::VSHL: in SimplifyDemandedVectorEltsForTargetNode()
50414 assert((X86ISD::VSHL == N->getOpcode() || X86ISD::VSRA == N->getOpcode() || in combineVectorShiftVar()
58771 case X86ISD::VSHL: in combineConcatVectorOps()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsARM.td573 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
574 // operation cannot be safely translated to LLVM's shift operators. VSHL can
581 // shifts, where the constant is replicated. For consistency with VSHL (and
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57.td1127 "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1131 "VSHL(s|u)(v16i8|v8i16|v4i32|v2i64)")>;
H A DARMScheduleSwift.td561 "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF", "VBIT",
H A DARMInstrNEON.td5915 // VSHL : Vector Shift
5960 // VSHL : Vector Shift Left (Immediate)
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td392 def VSHL : SInst<"vshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2591 case AArch64ISD::VSHL: { in computeKnownBitsForTargetNode()
14559 (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR || in tryLowerToSLI()
14566 (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR || in tryLowerToSLI()
15811 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0), in LowerVectorSRA_SRL_SHL()
21620 Opcode = AArch64ISD::VSHL; in tryCombineShiftImm()
23420 Op.getOpcode() == AArch64ISD::VSHL && in performVectorShiftCombine()
30222 case AArch64ISD::VSHL: { in SimplifyDemandedBitsForTargetNode()
H A DAArch64ISelDAGToDAG.cpp4688 if (N0->getOpcode() != AArch64ISD::VSHL || in trySelectXAR()
H A DAArch64InstrInfo.td902 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;