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Searched refs:VSHL (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h409 X86_INTRINSIC_DATA(avx2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0),
410 X86_INTRINSIC_DATA(avx2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0),
411 X86_INTRINSIC_DATA(avx2_psll_w, INTR_TYPE_2OP, X86ISD::VSHL, 0),
954 X86_INTRINSIC_DATA(avx512_psll_d_512, INTR_TYPE_2OP, X86ISD::VSHL, 0),
955 X86_INTRINSIC_DATA(avx512_psll_q_512, INTR_TYPE_2OP, X86ISD::VSHL, 0),
956 X86_INTRINSIC_DATA(avx512_psll_w_512, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1556 X86_INTRINSIC_DATA(sse2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1557 X86_INTRINSIC_DATA(sse2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1558 X86_INTRINSIC_DATA(sse2_psll_w, INTR_TYPE_2OP, X86ISD::VSHL, 0),
H A DX86ISelLowering.h356 VSHL, enumerator
H A DX86InstrFragmentsSIMD.td234 def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>;
H A DX86ISelLowering.cpp25164 case X86ISD::VSHL: in getTargetVShiftUniformOpcode()
25166 return IsVariable ? X86ISD::VSHL : X86ISD::VSHLI; in getTargetVShiftUniformOpcode()
33794 NODE_NAME_CASE(VSHL) in getTargetNodeName()
41228 case X86ISD::VSHL: in combineTargetShuffle()
41960 case X86ISD::VSHL: in SimplifyDemandedVectorEltsForTargetNode()
41972 return (UseOpc == X86ISD::VSHL || UseOpc == X86ISD::VSRL || in SimplifyDemandedVectorEltsForTargetNode()
42450 case X86ISD::VSHL: in SimplifyDemandedVectorEltsForTargetNode()
48659 assert((X86ISD::VSHL == N->getOpcode() || X86ISD::VSRA == N->getOpcode() || in combineVectorShiftVar()
56438 case X86ISD::VSHL: in combineConcatVectorOps()
57850 case X86ISD::VSHL: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsARM.td576 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
577 // operation cannot be safely translated to LLVM's shift operators. VSHL can
584 // shifts, where the constant is replicated. For consistency with VSHL (and
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h224 VSHL, enumerator
H A DAArch64ISelLowering.cpp2352 case AArch64ISD::VSHL: { in computeKnownBitsForTargetNode()
2645 MAKE_CASE(AArch64ISD::VSHL) in getTargetNodeName()
13709 (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR || in tryLowerToSLI()
13716 (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR || in tryLowerToSLI()
14906 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0), in LowerVectorSRA_SRL_SHL()
20879 Opcode = AArch64ISD::VSHL; in tryCombineShiftImm()
22389 Op.getOpcode() == AArch64ISD::VSHL && in performVectorShiftCombine()
28393 case AArch64ISD::VSHL: { in SimplifyDemandedBitsForTargetNode()
H A DAArch64ISelDAGToDAG.cpp4538 if (N0->getOpcode() != AArch64ISD::VSHL || in trySelectXAR()
H A DAArch64InstrInfo.td772 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57.td1127 "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1131 "VSHL(s|u)(v16i8|v8i16|v4i32|v2i64)")>;
H A DARMScheduleSwift.td561 "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF", "VBIT",
H A DARMInstrNEON.td5921 // VSHL : Vector Shift
5966 // VSHL : Vector Shift Left (Immediate)
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td396 def VSHL : SInst<"vshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;