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Searched refs:VReg (Results 1 – 25 of 147) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg() local
38 VRegDefMap[Key] = VReg; in getOrCreateVReg()
39 VRegUpwardsUse[Key] = VReg; in getOrCreateVReg()
40 return VReg; in getOrCreateVReg()
46 const Value *Val, Register VReg) { in setCurrentVReg() argument
47 VRegDefMap[std::make_pair(MBB, Val)] = VReg; in setCurrentVReg()
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt() local
60 VRegDefUses[Key] = VReg; in getOrCreateVRegDefAt()
61 setCurrentVReg(MBB, Val, VReg); in getOrCreateVRegDefAt()
62 return VReg; in getOrCreateVRegDefAt()
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H A DMIRVRegNamerUtils.cpp47 for (const auto &VReg : VRegs) { in getVRegRenameMap() local
48 const Register Reg = VReg.getReg(); in getVRegRenameMap()
49 VRM[Reg] = createVirtualRegisterWithLowerName(Reg, GetUniqueVRegName(VReg)); in getVRegRenameMap()
139 Register VRegRenamer::createVirtualRegister(Register VReg) { in createVirtualRegister() argument
140 assert(VReg.isVirtual() && "Expected Virtual Registers"); in createVirtualRegister()
141 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister()
142 return createVirtualRegisterWithLowerName(VReg, Name); in createVirtualRegister()
166 Register VRegRenamer::createVirtualRegisterWithLowerName(Register VReg, in createVirtualRegisterWithLowerName() argument
169 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in createVirtualRegisterWithLowerName()
171 : MRI.createGenericVirtualRegister(MRI.getType(VReg), LowerName); in createVirtualRegisterWithLowerName()
H A DLiveRangeEdit.cpp36 Register VReg = MRI.cloneVirtualRegister(OldReg); in createEmptyIntervalFrom() local
38 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createEmptyIntervalFrom()
40 LiveInterval &LI = LIS.createEmptyInterval(VReg); in createEmptyIntervalFrom()
56 Register VReg = MRI.cloneVirtualRegister(OldReg); in createFrom() local
58 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createFrom()
67 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
68 return VReg; in createFrom()
450 Register VReg = LI->reg(); in eliminateDeadDefs() local
452 TheDelegate->LRE_WillShrinkVirtReg(VReg); in eliminateDeadDefs()
460 if (llvm::is_contained(RegsBeingSpilled, VReg)) in eliminateDeadDefs()
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H A DRegAllocPBQP.cpp165 void spillVReg(Register VReg, SmallVectorImpl<Register> &NewIntervals,
330 Register VReg = G.getNodeMetadata(NId).getVReg(); in apply() local
331 LiveInterval &LI = LIS.getInterval(VReg); in apply()
601 Register VReg = Worklist.back(); in initializeGraph() local
604 LiveInterval &VRegLI = LIS.getInterval(VReg); in initializeGraph()
614 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph()
651 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller); in initializeGraph()
656 VRegAllowedMap[VReg.id()] = std::move(VRegAllowed); in initializeGraph()
660 auto VReg = KV.first; in initializeGraph() local
663 if (LIS.getInterval(VReg).empty()) { in initializeGraph()
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H A DLiveIntervalUnion.cpp159 const LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
160 if (VReg != RecentReg && !isSeenInterference(VReg)) { in collectInterferingVRegs()
161 RecentReg = VReg; in collectInterferingVRegs()
162 InterferingVRegs.push_back(VReg); in collectInterferingVRegs()
H A DRegisterScavenging.cpp339 Register VReg, bool ReserveAfter) { in scavengeVReg() argument
346 for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) { in scavengeVReg()
353 if (!MI.readsRegister(VReg, &TRI)) { in scavengeVReg()
370 MRI.def_operands(VReg), [VReg, &TRI](const MachineOperand &MO) { in scavengeVReg()
371 return !MO.getParent()->readsRegister(VReg, &TRI); in scavengeVReg()
380 const TargetRegisterClass &RC = *MRI.getRegClass(VReg); in scavengeVReg()
383 MRI.replaceRegWith(VReg, SReg); in scavengeVReg()
H A DMachineRegisterInfo.cpp178 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, in cloneVirtualRegister() argument
181 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister()
182 setType(Reg, getType(VReg)); in cloneVirtualRegister()
183 noteCloneVirtualRegister(Reg, VReg); in cloneVirtualRegister()
187 void MachineRegisterInfo::setType(Register VReg, LLT Ty) { in setType() argument
188 VRegToType.grow(VReg); in setType()
189 VRegToType[VReg] = Ty; in setType()
464 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { in getLiveInPhysReg()
466 if (LI.second == VReg) in getLiveInPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegNumbering.cpp88 Register VReg = Register::index2VirtReg(VRegIdx); in runOnMachineFunction() local
90 if (MRI.use_empty(VReg)) in runOnMachineFunction()
93 if (MFI.isVRegStackified(VReg)) { in runOnMachineFunction()
94 LLVM_DEBUG(dbgs() << "VReg " << printReg(VReg) << " -> WAReg " in runOnMachineFunction()
96 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++); in runOnMachineFunction()
99 if (MFI.getWAReg(VReg) == WebAssembly::UnusedReg) { in runOnMachineFunction()
100 LLVM_DEBUG(dbgs() << "VReg " << printReg(VReg) << " -> WAReg " << CurReg in runOnMachineFunction()
102 MFI.setWAReg(VReg, CurReg++); in runOnMachineFunction()
H A DWebAssemblyReplacePhysRegs.cpp84 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction() local
88 if (VReg == WebAssembly::NoRegister) { in runOnMachineFunction()
89 VReg = MRI.createVirtualRegister(RC); in runOnMachineFunction()
93 FI->setFrameBaseVreg(VReg); in runOnMachineFunction()
95 dbgs() << "replacing preg " << PReg << " with " << VReg << " (" in runOnMachineFunction()
96 << Register(VReg).virtRegIndex() << ")\n"; in runOnMachineFunction()
100 MO.setReg(VReg); in runOnMachineFunction()
H A DWebAssemblyMachineFunctionInfo.h122 void stackifyVReg(MachineRegisterInfo &MRI, Register VReg) { in stackifyVReg() argument
123 assert(MRI.getUniqueVRegDef(VReg)); in stackifyVReg()
124 auto I = VReg.virtRegIndex(); in stackifyVReg()
129 void unstackifyVReg(Register VReg) { in unstackifyVReg() argument
130 auto I = VReg.virtRegIndex(); in unstackifyVReg()
134 bool isVRegStackified(Register VReg) const { in isVRegStackified() argument
135 auto I = VReg.virtRegIndex(); in isVRegStackified()
142 void setWAReg(Register VReg, unsigned WAReg) { in setWAReg() argument
144 auto I = VReg.virtRegIndex(); in setWAReg()
148 unsigned getWAReg(Register VReg) const { in getWAReg() argument
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H A DWebAssemblyRegColoring.cpp67 unsigned VReg) { in computeWeight() argument
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
252 Register VReg = Register::index2VirtReg(I); in runOnMachineFunction() local
253 if (MFI.isVRegStackified(VReg)) in runOnMachineFunction()
256 if (MRI->use_empty(VReg)) in runOnMachineFunction()
259 LiveInterval *LI = &Liveness->getInterval(VReg); in runOnMachineFunction()
261 LI->setWeight(computeWeight(MRI, MBFI, VReg)); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h225 bool shouldTrackSubRegLiveness(Register VReg) const { in shouldTrackSubRegLiveness() argument
226 assert(VReg.isVirtual() && "Must pass a VReg"); in shouldTrackSubRegLiveness()
227 const TargetRegisterClass *RC = getRegClassOrNull(VReg); in shouldTrackSubRegLiveness()
764 LLVM_ABI Register cloneVirtualRegister(Register VReg, StringRef Name = "");
775 LLVM_ABI void setType(Register VReg, LLT Ty);
801 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) { in setRegAllocationHint() argument
802 assert(VReg.isVirtual()); in setRegAllocationHint()
804 auto &Hint = RegAllocHints[VReg]; in setRegAllocationHint()
812 void addRegAllocationHint(Register VReg, Register PrefReg) { in addRegAllocationHint() argument
813 assert(VReg.isVirtual()); in addRegAllocationHint()
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H A DRegAllocPBQP.h148 void setNodeIdForVReg(Register VReg, GraphBase::NodeId NId) { in setNodeIdForVReg() argument
149 VRegToNodeId[VReg.id()] = NId; in setNodeIdForVReg()
152 GraphBase::NodeId getNodeIdForVReg(Register VReg) const { in getNodeIdForVReg() argument
153 auto VRegItr = VRegToNodeId.find(VReg); in getNodeIdForVReg()
187 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg), in NodeMetadata()
203 void setVReg(Register VReg) { this->VReg = VReg; } in setVReg() argument
204 Register getVReg() const { return VReg; } in getVReg()
262 Register VReg; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURewriteAGPRCopyMFMA.cpp105 Register VReg = Register::index2VirtReg(I); in run() local
106 Register PhysReg = VRM.getPhys(VReg); in run()
111 const TargetRegisterClass *VirtRegRC = MRI.getRegClass(VReg); in run()
119 LiveInterval &LI = LIS.getInterval(VReg); in run()
154 << " Dst=[" << printReg(VReg) << " => " in run()
205 MRI.setRegClass(VReg, AssignedRC); in run()
211 MRI.replaceRegWith(CopySrcReg, VReg); in run()
225 LIS.removeInterval(VReg); in run()
226 LIS.createAndComputeVirtRegInterval(VReg); in run()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp275 Register VReg = MRI->createVirtualRegister(RC); in getVR() local
277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
278 return VReg; in getVR()
325 Register VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
349 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
356 .addReg(VReg); in AddRegisterOperand()
357 VReg = NewVReg; in AddRegisterOperand()
390 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
409 Register VReg = R->getReg(); in AddOperand() local
421 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) { in AddOperand()
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H A DSDNodeDbgValue.h69 return u.VReg; in getVReg()
78 static SDDbgOperand fromVReg(Register VReg) { in fromVReg() argument
79 return SDDbgOperand(VReg.id(), VREG); in fromVReg()
111 unsigned VReg; ///< Valid for registers. member
126 u.VReg = VRegOrFrameIdx; in SDDbgOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h280 SPIRVType *assignTypeToVReg(const Type *Type, Register VReg,
284 SPIRVType *assignIntTypeToVReg(unsigned BitWidth, Register VReg,
286 SPIRVType *assignFloatTypeToVReg(unsigned BitWidth, Register VReg,
289 Register VReg, MachineInstr &I,
294 void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg,
341 SPIRVType *getSPIRVTypeForVReg(Register VReg,
345 SPIRVType *getResultType(Register VReg, MachineFunction *MF = nullptr);
348 bool hasSPIRVTypeForVReg(Register VReg) const { in hasSPIRVTypeForVReg() argument
349 return getSPIRVTypeForVReg(VReg) != nullptr; in hasSPIRVTypeForVReg()
370 bool isScalarOfType(Register VReg, unsigned TypeOpcode) const;
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp266 Register VReg = Register::index2VirtReg(I); in selectMachineFunction() local
269 if (!MRI.def_empty(VReg)) in selectMachineFunction()
270 MI = &*MRI.def_instr_begin(VReg); in selectMachineFunction()
271 else if (!MRI.use_empty(VReg)) { in selectMachineFunction()
272 MI = &*MRI.use_instr_begin(VReg); in selectMachineFunction()
280 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in selectMachineFunction()
287 const LLT Ty = MRI.getType(VReg); in selectMachineFunction()
H A DUtils.cpp294 std::optional<APInt> llvm::getIConstantVRegVal(Register VReg, in getIConstantVRegVal() argument
297 VReg, MRI, /*LookThroughInstrs*/ false); in getIConstantVRegVal()
298 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && in getIConstantVRegVal()
314 llvm::getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI) { in getIConstantVRegSExtVal() argument
315 std::optional<APInt> Val = getIConstantVRegVal(VReg, MRI); in getIConstantVRegSExtVal()
336 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, in getConstantVRegValWithLookThrough() argument
342 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) && in getConstantVRegValWithLookThrough()
355 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
358 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
359 if (VReg.isPhysical()) in getConstantVRegValWithLookThrough()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h181 getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI);
185 getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI);
188 LLVM_ABI const APInt &getIConstantFromReg(Register VReg,
195 Register VReg; member
201 getIConstantVRegValWithLookThrough(Register VReg,
208 Register VReg, const MachineRegisterInfo &MRI,
213 Register VReg; member
219 getFConstantVRegValWithLookThrough(Register VReg,
223 LLVM_ABI const ConstantFP *getConstantFPVRegVal(Register VReg,
453 getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.h260 void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) { in addLiveInAttr() argument
261 LiveInAttrs.push_back(std::make_pair(VReg, Flags)); in addLiveInAttr()
266 bool isLiveInSExt(Register VReg) const;
270 bool isLiveInZExt(Register VReg) const;
H A DPPCMachineFunctionInfo.cpp62 bool PPCFunctionInfo::isLiveInSExt(Register VReg) const { in isLiveInSExt()
64 if (LiveIn.first == VReg) in isLiveInSExt()
69 bool PPCFunctionInfo::isLiveInZExt(Register VReg) const { in isLiveInZExt()
71 if (LiveIn.first == VReg) in isLiveInZExt()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td169 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
170 VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
172 VReg vrclass = regclass;
173 VReg wvrclass = wregclass;
174 VReg f8vrclass = f8regclass;
175 VReg f4vrclass = f4regclass;
176 VReg f2vrclass = f2regclass;
275 VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
291 VReg RegClass = M.vrclass;
748 class GetVRegNoV0<VReg VRegClass> {
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp679 for (const auto &VReg : YamlMF.VirtualRegisters) { in parseRegisterInfo() local
680 VRegInfo &Info = PFS.getVRegInfo(VReg.ID.Value); in parseRegisterInfo()
682 return error(VReg.ID.SourceRange.Start, in parseRegisterInfo()
684 Twine(VReg.ID.Value) + "'"); in parseRegisterInfo()
687 if (VReg.Class.Value == "_") { in parseRegisterInfo()
691 const auto *RC = Target->getRegClass(VReg.Class.Value); in parseRegisterInfo()
696 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo()
699 VReg.Class.SourceRange.Start, in parseRegisterInfo()
701 VReg.Class.Value + "'"); in parseRegisterInfo()
707 if (!VReg.PreferredRegister.Value.empty()) { in parseRegisterInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp912 Register VReg = MI.getOperand(0).getReg(); in getInstrMapping() local
913 if (!VReg) in getInstrMapping()
915 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
923 Register VReg = MI.getOperand(1).getReg(); in getInstrMapping() local
924 if (!VReg) in getInstrMapping()
926 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
984 Register VReg = MI.getOperand(Idx).getReg(); in getInstrMapping() local
985 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
986 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
1064 Register VReg = MI.getOperand(1).getReg(); in getInstrMapping() local
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