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Searched refs:VReg (Results 1 – 25 of 144) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg() local
38 VRegDefMap[Key] = VReg; in getOrCreateVReg()
39 VRegUpwardsUse[Key] = VReg; in getOrCreateVReg()
40 return VReg; in getOrCreateVReg()
46 const Value *Val, Register VReg) { in setCurrentVReg() argument
47 VRegDefMap[std::make_pair(MBB, Val)] = VReg; in setCurrentVReg()
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt() local
60 VRegDefUses[Key] = VReg; in getOrCreateVRegDefAt()
61 setCurrentVReg(MBB, Val, VReg); in getOrCreateVRegDefAt()
62 return VReg; in getOrCreateVRegDefAt()
72 Register VReg = getOrCreateVReg(MBB, Val); getOrCreateVRegUseAt() local
133 Register VReg = MF->getRegInfo().createVirtualRegister(RC); createEntriesInEntryBlock() local
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H A DMIRVRegNamerUtils.cpp49 for (const auto &VReg : VRegs) { in getVRegRenameMap() local
50 const unsigned Reg = VReg.getReg(); in getVRegRenameMap()
51 VRM[Reg] = createVirtualRegisterWithLowerName(Reg, GetUniqueVRegName(VReg)); in getVRegRenameMap()
141 unsigned VRegRenamer::createVirtualRegister(unsigned VReg) { in createVirtualRegister() argument
142 assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers"); in createVirtualRegister()
143 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister()
144 return createVirtualRegisterWithLowerName(VReg, Name); in createVirtualRegister()
168 unsigned VRegRenamer::createVirtualRegisterWithLowerName(unsigned VReg, in createVirtualRegisterWithLowerName() argument
171 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in createVirtualRegisterWithLowerName()
173 : MRI.createGenericVirtualRegister(MRI.getType(VReg), LowerName); in createVirtualRegisterWithLowerName()
H A DLiveRangeEdit.cpp36 Register VReg = MRI.cloneVirtualRegister(OldReg); in createEmptyIntervalFrom() local
38 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createEmptyIntervalFrom()
40 LiveInterval &LI = LIS.createEmptyInterval(VReg); in createEmptyIntervalFrom()
56 Register VReg = MRI.cloneVirtualRegister(OldReg); in createFrom() local
58 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createFrom()
67 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
68 return VReg; in createFrom()
453 Register VReg = LI->reg(); in eliminateDeadDefs() local
455 TheDelegate->LRE_WillShrinkVirtReg(VReg); in eliminateDeadDefs()
463 if (llvm::is_contained(RegsBeingSpilled, VReg)) in eliminateDeadDefs()
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H A DRegAllocPBQP.cpp168 void spillVReg(Register VReg, SmallVectorImpl<Register> &NewIntervals,
333 Register VReg = G.getNodeMetadata(NId).getVReg(); in apply() local
334 LiveInterval &LI = LIS.getInterval(VReg); in apply()
604 Register VReg = Worklist.back(); in initializeGraph() local
607 LiveInterval &VRegLI = LIS.getInterval(VReg); in initializeGraph()
617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph()
654 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller); in initializeGraph()
659 VRegAllowedMap[VReg.id()] = std::move(VRegAllowed); in initializeGraph()
663 auto VReg = KV.first; in initializeGraph() local
666 if (LIS.getInterval(VReg).empty()) { in initializeGraph()
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H A DLiveIntervalUnion.cpp159 const LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs()
160 if (VReg != RecentReg && !isSeenInterference(VReg)) { in collectInterferingVRegs() local
161 RecentReg = VReg; in collectInterferingVRegs()
162 InterferingVRegs.push_back(VReg); in collectInterferingVRegs()
H A DMachineRegisterInfo.cpp181 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, in cloneVirtualRegister() argument
184 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister()
185 setType(Reg, getType(VReg)); in cloneVirtualRegister()
186 noteCloneVirtualRegister(Reg, VReg); in cloneVirtualRegister()
190 void MachineRegisterInfo::setType(Register VReg, LLT Ty) { in setType() argument
191 VRegToType.grow(VReg); in setType()
192 VRegToType[VReg] = Ty; in setType()
460 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { in getLiveInPhysReg()
462 if (LI.second == VReg) in getLiveInPhysReg()
H A DRegisterScavenging.cpp334 /// Allocate a register for the virtual register \p VReg. The last use of in findSurvivorBackwards()
335 /// \p VReg is around the current position of the register scavenger \p RS. in findSurvivorBackwards()
340 Register VReg, bool ReserveAfter) { in findSurvivorBackwards()
347 for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) { in findSurvivorBackwards()
354 if (!MI.readsRegister(VReg, &TRI)) { in findSurvivorBackwards()
371 MRI.def_operands(VReg), [VReg, &TRI](const MachineOperand &MO) { in getFrameIndexOperandNum()
372 return !MO.getParent()->readsRegister(VReg, &TRI); in getFrameIndexOperandNum()
381 const TargetRegisterClass &RC = *MRI.getRegClass(VReg); in spill()
384 MRI.replaceRegWith(VReg, SRe in spill()
495 scavengeVReg(MachineRegisterInfo & MRI,RegScavenger & RS,Register VReg,bool ReserveAfter) scavengeVReg() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegNumbering.cpp79 LLVM_DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg() in runOnMachineFunction()
92 Register VReg = Register::index2VirtReg(VRegIdx); in runOnMachineFunction() local
94 if (MRI.use_empty(VReg)) in runOnMachineFunction()
97 if (MFI.isVRegStackified(VReg)) { in runOnMachineFunction()
98 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " in runOnMachineFunction()
100 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++); in runOnMachineFunction()
103 if (MFI.getWAReg(VReg) == WebAssembly::UnusedReg) { in runOnMachineFunction()
104 LLVM_DEBUG(dbgs() << "VReg " << VReg << " in runOnMachineFunction()
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H A DWebAssemblyReplacePhysRegs.cpp84 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction() local
88 if (VReg == WebAssembly::NoRegister) { in runOnMachineFunction()
89 VReg = MRI.createVirtualRegister(RC); in runOnMachineFunction()
93 FI->setFrameBaseVreg(VReg); in runOnMachineFunction()
95 dbgs() << "replacing preg " << PReg << " with " << VReg << " (" in runOnMachineFunction()
96 << Register::virtReg2Index(VReg) << ")\n"; in runOnMachineFunction()
100 MO.setReg(VReg); in runOnMachineFunction()
H A DWebAssemblyMachineFunctionInfo.h122 void stackifyVReg(MachineRegisterInfo &MRI, unsigned VReg) { in stackifyVReg() argument
123 assert(MRI.getUniqueVRegDef(VReg)); in stackifyVReg()
124 auto I = Register::virtReg2Index(VReg); in stackifyVReg()
129 void unstackifyVReg(unsigned VReg) { in unstackifyVReg() argument
130 auto I = Register::virtReg2Index(VReg); in unstackifyVReg()
134 bool isVRegStackified(unsigned VReg) const { in isVRegStackified() argument
135 auto I = Register::virtReg2Index(VReg); in isVRegStackified()
142 void setWAReg(unsigned VReg, unsigned WAReg) { in setWAReg() argument
144 auto I = Register::virtReg2Index(VReg); in setWAReg()
148 unsigned getWAReg(unsigned VReg) const { in getWAReg() argument
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H A DWebAssemblyRegColoring.cpp67 unsigned VReg) { in computeWeight() argument
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
252 Register VReg = Register::index2VirtReg(I); in runOnMachineFunction() local
253 if (MFI.isVRegStackified(VReg)) in runOnMachineFunction()
256 if (MRI->use_empty(VReg)) in runOnMachineFunction()
259 LiveInterval *LI = &Liveness->getInterval(VReg); in runOnMachineFunction()
261 LI->setWeight(computeWeight(MRI, MBFI, VReg)); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h230 bool shouldTrackSubRegLiveness(Register VReg) const { in shouldTrackSubRegLiveness() argument
231 assert(VReg.isVirtual() && "Must pass a VReg"); in shouldTrackSubRegLiveness()
232 const TargetRegisterClass *RC = getRegClassOrNull(VReg); in shouldTrackSubRegLiveness()
765 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
776 void setType(Register VReg, LLT Ty);
802 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) { in setRegAllocationHint() argument
803 assert(VReg.isVirtual()); in setRegAllocationHint()
804 RegAllocHints[VReg].first = Type; in setRegAllocationHint()
805 RegAllocHints[VReg].second.clear(); in setRegAllocationHint()
806 RegAllocHints[VReg].second.push_back(PrefReg); in setRegAllocationHint()
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H A DRegAllocPBQP.h148 void setNodeIdForVReg(Register VReg, GraphBase::NodeId NId) { in setNodeIdForVReg() argument
149 VRegToNodeId[VReg.id()] = NId; in setNodeIdForVReg()
152 GraphBase::NodeId getNodeIdForVReg(Register VReg) const { in getNodeIdForVReg() argument
153 auto VRegItr = VRegToNodeId.find(VReg); in getNodeIdForVReg()
187 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg), in NodeMetadata()
203 void setVReg(Register VReg) { this->VReg = VReg; } in setVReg() argument
204 Register getVReg() const { return VReg; } in getVReg()
262 Register VReg; variable
H A DScheduleDAGInstrs.h57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) in VReg2SUnit()
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
69 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, in VReg2SUnitOperIdx()
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp277 Register VReg = MRI->createVirtualRegister(RC); in getVR() local
279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
280 return VReg; in getVR()
327 Register VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
351 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
357 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
358 VReg = NewVReg; in AddRegisterOperand()
391 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
412 Register VReg = R->getReg(); in AddOperand() local
424 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) { in AddOperand()
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H A DSDNodeDbgValue.h68 return u.VReg; in getVReg()
77 static SDDbgOperand fromVReg(unsigned VReg) { in fromVReg() argument
78 return SDDbgOperand(VReg, VREG); in fromVReg()
110 unsigned VReg; ///< Valid for registers. member
125 u.VReg = VRegOrFrameIdx; in SDDbgOperand()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp256 Register VReg = Register::index2VirtReg(I); in runOnMachineFunction() local
259 if (!MRI.def_empty(VReg)) in runOnMachineFunction()
260 MI = &*MRI.def_instr_begin(VReg); in runOnMachineFunction()
261 else if (!MRI.use_empty(VReg)) { in runOnMachineFunction()
262 MI = &*MRI.use_instr_begin(VReg); in runOnMachineFunction()
270 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in runOnMachineFunction()
277 const LLT Ty = MRI.getType(VReg); in runOnMachineFunction()
H A DUtils.cpp295 std::optional<APInt> llvm::getIConstantVRegVal(Register VReg, in getIConstantVRegVal() argument
298 VReg, MRI, /*LookThroughInstrs*/ false); in getIConstantVRegVal()
299 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && in getIConstantVRegVal()
307 llvm::getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI) { in getIConstantVRegSExtVal() argument
308 std::optional<APInt> Val = getIConstantVRegVal(VReg, MRI); in getIConstantVRegSExtVal()
329 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, in getConstantVRegValWithLookThrough() argument
335 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) && in getConstantVRegValWithLookThrough()
348 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
351 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
352 if (VReg.isPhysical()) in getConstantVRegValWithLookThrough()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h274 SPIRVType *assignTypeToVReg(const Type *Type, Register VReg,
279 SPIRVType *assignIntTypeToVReg(unsigned BitWidth, Register VReg,
281 SPIRVType *assignFloatTypeToVReg(unsigned BitWidth, Register VReg,
284 Register VReg, MachineInstr &I,
289 void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg,
328 SPIRVType *getSPIRVTypeForVReg(Register VReg,
332 bool hasSPIRVTypeForVReg(Register VReg) const { in hasSPIRVTypeForVReg() argument
333 return getSPIRVTypeForVReg(VReg) != nullptr; in hasSPIRVTypeForVReg()
354 bool isScalarOfType(Register VReg, unsigned TypeOpcode) const;
359 bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const;
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h174 std::optional<APInt> getIConstantVRegVal(Register VReg,
178 std::optional<int64_t> getIConstantVRegSExtVal(Register VReg,
185 Register VReg; member
191 getIConstantVRegValWithLookThrough(Register VReg,
198 Register VReg, const MachineRegisterInfo &MRI,
203 Register VReg; member
209 getFConstantVRegValWithLookThrough(Register VReg,
213 const ConstantFP* getConstantFPVRegVal(Register VReg,
435 std::optional<FPValueAndVReg> getFConstantSplat(Register VReg,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td140 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
141 VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
143 VReg vrclass = regclass;
144 VReg wvrclass = wregclass;
145 VReg f8vrclass = f8regclass;
146 VReg f4vrclass = f4regclass;
147 VReg f2vrclas
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.h260 void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) { in addLiveInAttr() argument
261 LiveInAttrs.push_back(std::make_pair(VReg, Flags)); in addLiveInAttr()
266 bool isLiveInSExt(Register VReg) const;
270 bool isLiveInZExt(Register VReg) const;
H A DPPCMachineFunctionInfo.cpp62 bool PPCFunctionInfo::isLiveInSExt(Register VReg) const { in isLiveInSExt()
64 if (LiveIn.first == VReg) in isLiveInSExt()
69 bool PPCFunctionInfo::isLiveInZExt(Register VReg) const { in isLiveInZExt()
71 if (LiveIn.first == VReg) in isLiveInZExt()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp621 for (const auto &VReg : YamlMF.VirtualRegisters) { in parseRegisterInfo() local
622 VRegInfo &Info = PFS.getVRegInfo(VReg.ID.Value); in parseRegisterInfo()
624 return error(VReg.ID.SourceRange.Start, in parseRegisterInfo()
626 Twine(VReg.ID.Value) + "'"); in parseRegisterInfo()
629 if (VReg.Class.Value == "_") { in parseRegisterInfo()
633 const auto *RC = Target->getRegClass(VReg.Class.Value); in parseRegisterInfo()
638 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo()
641 VReg.Class.SourceRange.Start, in parseRegisterInfo()
643 VReg.Class.Value + "'"); in parseRegisterInfo()
649 if (!VReg.PreferredRegister.Value.empty()) { in parseRegisterInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp893 Register VReg = MI.getOperand(0).getReg(); in getInstrMapping() local
894 if (!VReg) in getInstrMapping()
896 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
904 Register VReg = MI.getOperand(1).getReg(); in getInstrMapping() local
905 if (!VReg) in getInstrMapping()
907 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
965 Register VReg = MI.getOperand(Idx).getReg(); in getInstrMapping() local
966 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
967 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
1043 Register VReg = MI.getOperand(1).getReg(); in getInstrMapping() local
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