Lines Matching refs:VReg

277     Register VReg = MRI->createVirtualRegister(RC);  in getVR()  local
279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
280 return VReg; in getVR()
327 Register VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
351 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
357 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
358 VReg = NewVReg; in AddRegisterOperand()
391 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
412 Register VReg = R->getReg(); in AddOperand() local
424 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) { in AddOperand()
427 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddOperand()
428 VReg = NewVReg; in AddOperand()
434 MIB.addReg(VReg, getImplRegState(Imp)); in AddOperand()
476 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg() argument
478 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
484 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); in ConstrainForSubReg()
488 return VReg; in ConstrainForSubReg()
496 .addReg(VReg); in ConstrainForSubReg()
638 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitCopyToRegClassNode() local
646 NewVReg).addReg(VReg); in EmitCopyToRegClassNode()
835 auto AddVRegOp = [&](unsigned VReg) { in EmitDbgInstrRef() argument
837 /* Reg */ VReg, /* isDef */ false, /* isImp */ false, in EmitDbgInstrRef()
848 unsigned VReg; in EmitDbgInstrRef() local
851 VReg = DbgOperand.getVReg(); in EmitDbgInstrRef()
855 if (!MRI->hasOneDef(VReg)) { in EmitDbgInstrRef()
856 AddVRegOp(VReg); in EmitDbgInstrRef()
860 DefMI = &*MRI->def_instr_begin(VReg); in EmitDbgInstrRef()
871 VReg = getVR(Op, VRBaseMap); in EmitDbgInstrRef()
875 if (!MRI->hasOneDef(VReg)) { in EmitDbgInstrRef()
876 AddVRegOp(VReg); in EmitDbgInstrRef()
880 DefMI = &*MRI->def_instr_begin(VReg); in EmitDbgInstrRef()
891 AddVRegOp(VReg); in EmitDbgInstrRef()
898 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg) in EmitDbgInstrRef()
1225 Register VReg = getVR(GluedNode->getOperand(0), VRBaseMap); in EmitMachineNode() local
1226 MachineOperand MO = MachineOperand::CreateReg(VReg, /*isDef=*/false, in EmitMachineNode()