| /freebsd/sys/contrib/openzfs/module/zfs/ |
| H A D | vdev_raidz_math_powerpc_altivec_common.h | 53 #define VR2(r...) VR2_(r, 36) macro
149 "vxor " VR2(r) "," VR2(r) ",19\n" \
179 "vxor " VR2(r) "," VR2(r) ",19\n" \
211 "vxor " VR6(r) "," VR6(r) "," VR2(r) "\n" \
218 "vxor " VR2(r) "," VR2(r) "," VR0(r) "\n" \
235 "vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
248 "vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
270 "vor " VR6(r) "," VR2(r) "," VR2(r) "\n" \
277 "vor " VR2(r) "," VR0(r) "," VR0(r) "\n" \
294 "lvx " VR2(r) " ,0,%[SRC2]\n" \
[all …]
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| H A D | vdev_raidz_math_aarch64_neon_common.h | 56 #define VR2(r...) VR2_(r, 36) macro
152 "eor " VR2(r) ".16b," VR2(r) ".16b,v19.16b\n" \
182 "eor " VR2(r) ".16b," VR2(r) ".16b,v19.16b\n" \
214 "eor " VR6(r) ".16b," VR6(r) ".16b," VR2(r) ".16b\n" \
221 "eor " VR2(r) ".16b," VR2(r) ".16b," VR0(r) ".16b\n" \
238 "eor " VR2(r) ".16b," VR2(r) ".16b," VR2(r) ".16b\n" \
251 "eor " VR2(r) ".16b," VR2(r) ".16b," VR2(r) ".16b\n" \
273 "mov " VR6(r) ".16b," VR2(r) ".16b\n" \
280 "mov " VR2(r) ".16b," VR0(r) ".16b\n" \
297 "ld1 { " VR2(r) ".4s },%[SRC2]\n" \
[all …]
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| H A D | vdev_raidz_math_avx2.c | 50 #define VR2(r...) VR2_(r, 1) macro
79 "vpxor 0x40(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
101 "vpxor %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
106 "vpxor %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
123 "vmovdqa %" VR2(r) ", %" VR6(r) "\n" \
128 "vmovdqa %" VR0(r) ", %" VR2(r) "\n" \
143 "vmovdqa 0x40(%[SRC]), %%" VR2(r) "\n" \
165 "vmovdqa %%" VR2(r) ", 0x40(%[DST])\n" \
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| H A D | vdev_raidz_math_avx512bw.c | 54 #define VR2(r...) VR2_(r, 1) macro
82 "vpxorq 0x80(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
104 "vpxorq %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
109 "vpxorq %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
126 "vmovdqa64 %" VR2(r) ", %" VR6(r) "\n" \
131 "vmovdqa64 %" VR0(r) ", %" VR2(r) "\n" \
146 "vmovdqa64 0x80(%[SRC]), %%" VR2(r) "\n" \
168 "vmovdqa64 %%" VR2(r) ", 0x80(%[DST])\n" \
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| H A D | vdev_raidz_math_ssse3.c | 51 #define VR2(r...) VR2_(r, 1) macro
80 "pxor 0x20(%[SRC]), %%" VR2(r) "\n" \
102 "pxor %" VR2(r) ", %" VR6(r) "\n" \
107 "pxor %" VR0(r) ", %" VR2(r) "\n" \
124 "movdqa %" VR2(r) ", %" VR6(r) "\n" \
129 "movdqa %" VR0(r) ", %" VR2(r) "\n" \
144 "movdqa 0x20(%[SRC]), %%" VR2(r) "\n" \
166 "movdqa %%" VR2(r)", 0x20(%[DST])\n" \
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| H A D | vdev_raidz_math_avx512f.c | 53 #define VR2(r...) VR2_(r, 1) macro
96 "vpxorq 0x80(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
110 "vpxorq %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
115 "vpxorq %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
132 "vmovdqa64 %" VR2(r) ", %" VR6(r) "\n" \
137 "vmovdqa64 %" VR0(r) ", %" VR2(r) "\n" \
150 "vmovdqa64 0x80(%[SRC]), %%" VR2(r) "\n" \
164 "vmovdqa64 %%" VR2(r) ", 0x80(%[DST])\n" \
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| H A D | vdev_raidz_math_sse2.c | 52 #define VR2(r...) VR2_(r, 1, 2, 3, 4, 5, 6) macro
72 "pxor 0x20(%[SRC]), %%" VR2(r) "\n" \
96 "pxor %" VR2(r) ", %" VR6(r) "\n" \
101 "pxor %" VR0(r) ", %" VR2(r) "\n" \
120 "movdqa %" VR2(r) ", %" VR6(r) "\n" \
125 "movdqa %" VR0(r) ", %" VR2(r) "\n" \
144 "movdqa 0x20(%[SRC]), %%" VR2(r) "\n" \
169 "movdqa %%" VR2(r)", 0x20(%[DST])\n" \
227 _MUL2_x2(VR2(r), VR3(r)); \
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 223 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
224 return operator[](VR1) < operator[](VR2); in operator ()()
298 bool operator() (unsigned VR1, unsigned VR2) const;
316 bool operator() (unsigned VR1, unsigned VR2) const;
327 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()()
337 if (VR1 == VR2) in operator ()()
340 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
351 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
354 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { in operator ()()
355 if (VR1 == VR2) in operator ()()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3061 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
3062 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) in emitBPOSGE32()
3074 .addReg(VR2) in emitBPOSGE32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4670 const MCPhysReg ArgVRs[] = {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,
|