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Searched refs:VR2 (Results 1 – 10 of 10) sorted by relevance

/freebsd/sys/contrib/openzfs/module/zfs/
H A Dvdev_raidz_math_powerpc_altivec_common.h43 #define VR2(r...) VR2_(r, 36) macro
139 "vxor " VR2(r) "," VR2(r) ",19\n" \
169 "vxor " VR2(r) "," VR2(r) ",19\n" \
201 "vxor " VR6(r) "," VR6(r) "," VR2(r) "\n" \
208 "vxor " VR2(r) "," VR2(r) "," VR0(r) "\n" \
225 "vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
238 "vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
260 "vor " VR6(r) "," VR2(r) "," VR2(r) "\n" \
267 "vor " VR2(r) "," VR0(r) "," VR0(r) "\n" \
284 "lvx " VR2(r) " ,0,%[SRC2]\n" \
[all …]
H A Dvdev_raidz_math_aarch64_neon_common.h46 #define VR2(r...) VR2_(r, 36) macro
142 "eor " VR2(r) ".16b," VR2(r) ".16b,v19.16b\n" \
172 "eor " VR2(r) ".16b," VR2(r) ".16b,v19.16b\n" \
204 "eor " VR6(r) ".16b," VR6(r) ".16b," VR2(r) ".16b\n" \
211 "eor " VR2(r) ".16b," VR2(r) ".16b," VR0(r) ".16b\n" \
228 "eor " VR2(r) ".16b," VR2(r) ".16b," VR2(r) ".16b\n" \
241 "eor " VR2(r) ".16b," VR2(r) ".16b," VR2(r) ".16b\n" \
263 "mov " VR6(r) ".16b," VR2(r) ".16b\n" \
270 "mov " VR2(r) ".16b," VR0(r) ".16b\n" \
287 "ld1 { " VR2(r) ".4s },%[SRC2]\n" \
[all …]
H A Dvdev_raidz_math_avx2.c41 #define VR2(r...) VR2_(r, 1) macro
70 "vpxor 0x40(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
92 "vpxor %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
97 "vpxor %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
114 "vmovdqa %" VR2(r) ", %" VR6(r) "\n" \
119 "vmovdqa %" VR0(r) ", %" VR2(r) "\n" \
134 "vmovdqa 0x40(%[SRC]), %%" VR2(r) "\n" \
156 "vmovdqa %%" VR2(r) ", 0x40(%[DST])\n" \
H A Dvdev_raidz_math_avx512bw.c44 #define VR2(r...) VR2_(r, 1) macro
72 "vpxorq 0x80(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
94 "vpxorq %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
99 "vpxorq %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
116 "vmovdqa64 %" VR2(r) ", %" VR6(r) "\n" \
121 "vmovdqa64 %" VR0(r) ", %" VR2(r) "\n" \
136 "vmovdqa64 0x80(%[SRC]), %%" VR2(r) "\n" \
158 "vmovdqa64 %%" VR2(r) ", 0x80(%[DST])\n" \
H A Dvdev_raidz_math_ssse3.c41 #define VR2(r...) VR2_(r, 1) macro
70 "pxor 0x20(%[SRC]), %%" VR2(r) "\n" \
92 "pxor %" VR2(r) ", %" VR6(r) "\n" \
97 "pxor %" VR0(r) ", %" VR2(r) "\n" \
114 "movdqa %" VR2(r) ", %" VR6(r) "\n" \
119 "movdqa %" VR0(r) ", %" VR2(r) "\n" \
134 "movdqa 0x20(%[SRC]), %%" VR2(r) "\n" \
156 "movdqa %%" VR2(r)", 0x20(%[DST])\n" \
H A Dvdev_raidz_math_avx512f.c43 #define VR2(r...) VR2_(r, 1) macro
86 "vpxorq 0x80(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
100 "vpxorq %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
105 "vpxorq %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
122 "vmovdqa64 %" VR2(r) ", %" VR6(r) "\n" \
127 "vmovdqa64 %" VR0(r) ", %" VR2(r) "\n" \
140 "vmovdqa64 0x80(%[SRC]), %%" VR2(r) "\n" \
154 "vmovdqa64 %%" VR2(r) ", 0x80(%[DST])\n" \
H A Dvdev_raidz_math_sse2.c42 #define VR2(r...) VR2_(r, 1, 2, 3, 4, 5, 6) macro
62 "pxor 0x20(%[SRC]), %%" VR2(r) "\n" \
86 "pxor %" VR2(r) ", %" VR6(r) "\n" \
91 "pxor %" VR0(r) ", %" VR2(r) "\n" \
110 "movdqa %" VR2(r) ", %" VR6(r) "\n" \
115 "movdqa %" VR0(r) ", %" VR2(r) "\n" \
134 "movdqa 0x20(%[SRC]), %%" VR2(r) "\n" \
159 "movdqa %%" VR2(r)", 0x20(%[DST])\n" \
217 _MUL2_x2(VR2(r), VR3(r)); \
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp224 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
225 return operator[](VR1) < operator[](VR2); in operator ()()
299 bool operator() (unsigned VR1, unsigned VR2) const;
317 bool operator() (unsigned VR1, unsigned VR2) const;
328 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()()
338 if (VR1 == VR2) in operator ()()
341 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
352 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
355 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { in operator ()()
356 if (VR1 == VR2) in operator ()()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3122 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
3123 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) in emitBPOSGE32()
3135 .addReg(VR2) in emitBPOSGE32()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp6648 const MCPhysReg ArgVRs[] = {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,