| /freebsd/sys/contrib/openzfs/module/zfs/ |
| H A D | vdev_raidz_math_avx2.c | 49 #define VR1(r...) VR1_(r) macro
78 "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
86 "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
100 "vpxor %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
107 "vpxor %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
122 "vmovdqa %" VR1(r) ", %" VR5(r) "\n" \
129 "vmovdqa %" VR1(r) ", %" VR3(r)); \
142 "vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
150 "vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
164 "vmovdqa %%" VR1(r) ", 0x20(%[DST])\n" \
[all …]
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| H A D | vdev_raidz_math_avx512bw.c | 53 #define VR1(r...) VR1_(r) macro
81 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
89 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
103 "vpxorq %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
110 "vpxorq %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
125 "vmovdqa64 %" VR1(r) ", %" VR5(r) "\n" \
132 "vmovdqa64 %" VR1(r) ", %" VR3(r)); \
145 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
153 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
167 "vmovdqa64 %%" VR1(r) ", 0x40(%[DST])\n" \
[all …]
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| H A D | vdev_raidz_math_ssse3.c | 50 #define VR1(r...) VR1_(r) macro
79 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
87 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
101 "pxor %" VR1(r) ", %" VR5(r) "\n" \
108 "pxor %" VR1(r) ", %" VR3(r)); \
123 "movdqa %" VR1(r) ", %" VR5(r) "\n" \
130 "movdqa %" VR1(r) ", %" VR3(r)); \
143 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
151 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
165 "movdqa %%" VR1(r)", 0x10(%[DST])\n" \
[all …]
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| H A D | vdev_raidz_math_powerpc_altivec_common.h | 52 #define VR1(r...) VR1_(r) macro
148 "vxor " VR1(r) "," VR1(r) ",20\n" \
178 "vxor " VR1(r) "," VR1(r) ",20\n" \
193 "vxor " VR1(r) "," VR1(r) ",20\n" \
210 "vxor " VR5(r) "," VR5(r) "," VR1(r) "\n" \
219 "vxor " VR3(r) "," VR3(r) "," VR1(r) "\n" \
234 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
247 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
255 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
269 "vor " VR5(r) "," VR1(r) "," VR1(r) "\n" \
[all …]
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| H A D | vdev_raidz_math_aarch64_neon_common.h | 55 #define VR1(r...) VR1_(r) macro
151 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
181 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
196 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
213 "eor " VR5(r) ".16b," VR5(r) ".16b," VR1(r) ".16b\n" \
222 "eor " VR3(r) ".16b," VR3(r) ".16b," VR1(r) ".16b\n" \
237 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
250 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
258 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
272 "mov " VR5(r) ".16b," VR1(r) ".16b\n" \
[all …]
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| H A D | vdev_raidz_math_avx512f.c | 52 #define VR1(r...) VR1_(r) macro
95 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
109 "vpxorq %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
116 "vpxorq %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
131 "vmovdqa64 %" VR1(r) ", %" VR5(r) "\n" \
138 "vmovdqa64 %" VR1(r) ", %" VR3(r)); \
149 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
163 "vmovdqa64 %%" VR1(r) ", 0x40(%[DST])\n" \
187 "vpandq %" VR1(r)", %zmm30, %zmm25\n" \
195 "vpsllq $1, %" VR1(r)", %" VR1(r) "\n" \
[all …]
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| H A D | vdev_raidz_math_sse2.c | 51 #define VR1(r...) VR1_(r, 1, 2, 3, 4, 5, 6) macro
71 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
79 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
95 "pxor %" VR1(r) ", %" VR5(r) "\n" \
102 "pxor %" VR1(r) ", %" VR3(r)); \
106 "pxor %" VR0(r) ", %" VR1(r)); \
119 "movdqa %" VR1(r) ", %" VR5(r) "\n" \
126 "movdqa %" VR1(r) ", %" VR3(r)); \
130 "movdqa %" VR0(r) ", %" VR1(r)); \
143 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 223 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
224 return operator[](VR1) < operator[](VR2); in operator ()()
298 bool operator() (unsigned VR1, unsigned VR2) const;
316 bool operator() (unsigned VR1, unsigned VR2) const;
327 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
337 if (VR1 == VR2) in operator ()()
340 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
351 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
354 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
355 if (VR1 == VR2) in operator ()()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 208 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() local
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
233 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() local
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
266 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() local
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
277 .addReg(VR1, RegState::Kill); in expandCopyACC()
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| H A D | MipsSEISelLowering.cpp | 3067 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
3068 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
3076 .addReg(VR1) in emitBPOSGE32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4670 const MCPhysReg ArgVRs[] = {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,
|