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Searched refs:VR1 (Results 1 – 12 of 12) sorted by relevance

/freebsd/sys/contrib/openzfs/module/zfs/
H A Dvdev_raidz_math_avx2.c40 #define VR1(r...) VR1_(r) macro
69 "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
77 "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
91 "vpxor %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
98 "vpxor %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
113 "vmovdqa %" VR1(r) ", %" VR5(r) "\n" \
120 "vmovdqa %" VR1(r) ", %" VR3(r)); \
133 "vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
141 "vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
155 "vmovdqa %%" VR1(r) ", 0x20(%[DST])\n" \
[all …]
H A Dvdev_raidz_math_avx512bw.c43 #define VR1(r...) VR1_(r) macro
71 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
79 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
93 "vpxorq %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
100 "vpxorq %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
115 "vmovdqa64 %" VR1(r) ", %" VR5(r) "\n" \
122 "vmovdqa64 %" VR1(r) ", %" VR3(r)); \
135 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
143 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
157 "vmovdqa64 %%" VR1(r) ", 0x40(%[DST])\n" \
[all …]
H A Dvdev_raidz_math_ssse3.c40 #define VR1(r...) VR1_(r) macro
69 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
77 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
91 "pxor %" VR1(r) ", %" VR5(r) "\n" \
98 "pxor %" VR1(r) ", %" VR3(r)); \
113 "movdqa %" VR1(r) ", %" VR5(r) "\n" \
120 "movdqa %" VR1(r) ", %" VR3(r)); \
133 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
141 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
155 "movdqa %%" VR1(r)", 0x10(%[DST])\n" \
[all …]
H A Dvdev_raidz_math_powerpc_altivec_common.h42 #define VR1(r...) VR1_(r) macro
138 "vxor " VR1(r) "," VR1(r) ",20\n" \
168 "vxor " VR1(r) "," VR1(r) ",20\n" \
183 "vxor " VR1(r) "," VR1(r) ",20\n" \
200 "vxor " VR5(r) "," VR5(r) "," VR1(r) "\n" \
209 "vxor " VR3(r) "," VR3(r) "," VR1(r) "\n" \
224 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
237 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
245 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
259 "vor " VR5(r) "," VR1(r) "," VR1(r) "\n" \
[all …]
H A Dvdev_raidz_math_aarch64_neon_common.h45 #define VR1(r...) VR1_(r) macro
141 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
171 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
186 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
203 "eor " VR5(r) ".16b," VR5(r) ".16b," VR1(r) ".16b\n" \
212 "eor " VR3(r) ".16b," VR3(r) ".16b," VR1(r) ".16b\n" \
227 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
240 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
248 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
262 "mov " VR5(r) ".16b," VR1(r) ".16b\n" \
[all …]
H A Dvdev_raidz_math_avx512f.c42 #define VR1(r...) VR1_(r) macro
85 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
99 "vpxorq %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
106 "vpxorq %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
121 "vmovdqa64 %" VR1(r) ", %" VR5(r) "\n" \
128 "vmovdqa64 %" VR1(r) ", %" VR3(r)); \
139 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
153 "vmovdqa64 %%" VR1(r) ", 0x40(%[DST])\n" \
177 "vpandq %" VR1(r)", %zmm30, %zmm25\n" \
185 "vpsllq $1, %" VR1(r)", %" VR1(r) "\n" \
[all …]
H A Dvdev_raidz_math_sse2.c41 #define VR1(r...) VR1_(r, 1, 2, 3, 4, 5, 6) macro
61 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
69 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
85 "pxor %" VR1(r) ", %" VR5(r) "\n" \
92 "pxor %" VR1(r) ", %" VR3(r)); \
96 "pxor %" VR0(r) ", %" VR1(r)); \
109 "movdqa %" VR1(r) ", %" VR5(r) "\n" \
116 "movdqa %" VR1(r) ", %" VR3(r)); \
120 "movdqa %" VR0(r) ", %" VR1(r)); \
133 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp206 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() local
215 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
216 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
231 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() local
238 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
239 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
264 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() local
273 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
275 .addReg(VR1, RegState::Kill); in expandCopyACC()
H A DMipsSEISelLowering.cpp3128 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
3129 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
3137 .addReg(VR1) in emitBPOSGE32()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp224 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
225 return operator[](VR1) < operator[](VR2); in operator ()()
299 bool operator() (unsigned VR1, unsigned VR2) const;
317 bool operator() (unsigned VR1, unsigned VR2) const;
328 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
338 if (VR1 == VR2) in operator ()()
341 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
352 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
355 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
356 if (VR1 == VR2) in operator ()()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtso28 regulator-name = "VR1-1.8V";
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp6648 const MCPhysReg ArgVRs[] = {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,