| /freebsd/sys/contrib/openzfs/module/zfs/ |
| H A D | vdev_raidz_math_avx2.c | 48 #define VR1(r...) VR1_(r) macro
77 "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
85 "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
99 "vpxor %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
106 "vpxor %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
121 "vmovdqa %" VR1(r) ", %" VR5(r) "\n" \
128 "vmovdqa %" VR1(r) ", %" VR3(r)); \
141 "vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
149 "vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
163 "vmovdqa %%" VR1(r) ", 0x20(%[DST])\n" \
[all …]
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| H A D | vdev_raidz_math_avx512bw.c | 52 #define VR1(r...) VR1_(r) macro
80 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
88 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
102 "vpxorq %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
109 "vpxorq %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
124 "vmovdqa64 %" VR1(r) ", %" VR5(r) "\n" \
131 "vmovdqa64 %" VR1(r) ", %" VR3(r)); \
144 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
152 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
166 "vmovdqa64 %%" VR1(r) ", 0x40(%[DST])\n" \
[all …]
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| H A D | vdev_raidz_math_ssse3.c | 49 #define VR1(r...) VR1_(r) macro
78 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
86 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
100 "pxor %" VR1(r) ", %" VR5(r) "\n" \
107 "pxor %" VR1(r) ", %" VR3(r)); \
122 "movdqa %" VR1(r) ", %" VR5(r) "\n" \
129 "movdqa %" VR1(r) ", %" VR3(r)); \
142 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
150 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
164 "movdqa %%" VR1(r)", 0x10(%[DST])\n" \
[all …]
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| H A D | vdev_raidz_math_powerpc_altivec_common.h | 51 #define VR1(r...) VR1_(r) macro
147 "vxor " VR1(r) "," VR1(r) ",20\n" \
177 "vxor " VR1(r) "," VR1(r) ",20\n" \
192 "vxor " VR1(r) "," VR1(r) ",20\n" \
209 "vxor " VR5(r) "," VR5(r) "," VR1(r) "\n" \
218 "vxor " VR3(r) "," VR3(r) "," VR1(r) "\n" \
233 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
246 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
254 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
268 "vor " VR5(r) "," VR1(r) "," VR1(r) "\n" \
[all …]
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| H A D | vdev_raidz_math_aarch64_neon_common.h | 54 #define VR1(r...) VR1_(r) macro
150 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
180 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
195 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
212 "eor " VR5(r) ".16b," VR5(r) ".16b," VR1(r) ".16b\n" \
221 "eor " VR3(r) ".16b," VR3(r) ".16b," VR1(r) ".16b\n" \
236 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
249 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
257 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
271 "mov " VR5(r) ".16b," VR1(r) ".16b\n" \
[all …]
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| H A D | vdev_raidz_math_avx512f.c | 51 #define VR1(r...) VR1_(r) macro
94 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
108 "vpxorq %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
115 "vpxorq %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
130 "vmovdqa64 %" VR1(r) ", %" VR5(r) "\n" \
137 "vmovdqa64 %" VR1(r) ", %" VR3(r)); \
148 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
162 "vmovdqa64 %%" VR1(r) ", 0x40(%[DST])\n" \
186 "vpandq %" VR1(r)", %zmm30, %zmm25\n" \
194 "vpsllq $1, %" VR1(r)", %" VR1(r) "\n" \
[all …]
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| H A D | vdev_raidz_math_sse2.c | 50 #define VR1(r...) VR1_(r, 1, 2, 3, 4, 5, 6) macro
70 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
78 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
94 "pxor %" VR1(r) ", %" VR5(r) "\n" \
101 "pxor %" VR1(r) ", %" VR3(r)); \
105 "pxor %" VR0(r) ", %" VR1(r)); \
118 "movdqa %" VR1(r) ", %" VR5(r) "\n" \
125 "movdqa %" VR1(r) ", %" VR3(r)); \
129 "movdqa %" VR0(r) ", %" VR1(r)); \
142 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 223 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
224 return operator[](VR1) < operator[](VR2); in operator ()()
298 bool operator() (unsigned VR1, unsigned VR2) const;
316 bool operator() (unsigned VR1, unsigned VR2) const;
327 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
337 if (VR1 == VR2) in operator ()()
340 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
351 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
354 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
355 if (VR1 == VR2) in operator ()()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 208 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() local
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
233 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() local
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
266 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() local
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
277 .addReg(VR1, RegState::Kill); in expandCopyACC()
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| H A D | MipsSEISelLowering.cpp | 3067 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
3068 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
3076 .addReg(VR1) in emitBPOSGE32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4670 const MCPhysReg ArgVRs[] = {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,
|