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Searched refs:VMV_X_S (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp92 case RISCV::VMV_X_S: in getRISCVInstructionCost()
549 RISCV::VMV_X_S, RISCV::VMV_V_X, in getShuffleCost()
1216 Opcodes = {RISCV::VMV_S_X, RISCV::VREDMAX_VS, RISCV::VMV_X_S}; in getMinMaxReductionCost()
1220 Opcodes = {RISCV::VMV_S_X, RISCV::VREDMIN_VS, RISCV::VMV_X_S}; in getMinMaxReductionCost()
1224 Opcodes = {RISCV::VMV_S_X, RISCV::VREDMAXU_VS, RISCV::VMV_X_S}; in getMinMaxReductionCost()
1228 Opcodes = {RISCV::VMV_S_X, RISCV::VREDMINU_VS, RISCV::VMV_X_S}; in getMinMaxReductionCost()
1305 Opcodes = {RISCV::VMV_S_X, RISCV::VREDSUM_VS, RISCV::VMV_X_S}; in getArithmeticReductionCost()
1309 Opcodes = {RISCV::VMV_S_X, RISCV::VREDOR_VS, RISCV::VMV_X_S}; in getArithmeticReductionCost()
1313 Opcodes = {RISCV::VMV_S_X, RISCV::VREDXOR_VS, RISCV::VMV_X_S}; in getArithmeticReductionCost()
1317 Opcodes = {RISCV::VMV_S_X, RISCV::VREDAND_VS, RISCV::VMV_X_S}; in getArithmeticReductionCost()
H A DRISCVISelLowering.h172 VMV_X_S, enumerator
H A DRISCVInsertVSETVLI.cpp96 case RISCV::VMV_X_S: in isScalarExtractInstr()
H A DRISCVISelLowering.cpp8757 SDValue Elt0 = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec); in lowerEXTRACT_VECTOR_ELT()
9207 SDValue Res = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
12698 SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec); in ReplaceNodeResults()
12709 SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32); in ReplaceNodeResults()
12843 SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL, in ReplaceNodeResults()
12857 SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec); in ReplaceNodeResults()
12868 SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32); in ReplaceNodeResults()
17398 if (Val.getOpcode() == RISCVISD::VMV_X_S || in PerformDAGCombine()
17502 if (Scalar.getOpcode() == RISCVISD::VMV_X_S && Passthru.isUndef() && in PerformDAGCombine()
17529 case RISCVISD::VMV_X_S: { in PerformDAGCombine()
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H A DRISCVInstrInfoV.td1631 def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
H A DRISCVInstrInfoVPseudos.td73 def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S",
6762 let HasSEWOp = 1, BaseInstr = VMV_X_S in