| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSchedSiFive7.td | 29 /// Number of DLEN parts = (LMUL * VLEN) / DLEN.
30 /// Since DLEN = VLEN / 2, Num DLEN parts = 2 * LMUL.
76 // formula (2 * VLEN * LMUL) / DLEN = 4 * LMUL
91 class SiFive7GetCyclesSegmented<string mx, int sew, int nf, int VLEN> {
92 defvar DLEN = !div(VLEN, 2);
93 // (VLEN * LMUL) / SEW
95 !eq(mx, "M1") : !div(VLEN, sew),
96 !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),
97 !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),
98 !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),
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| H A D | RISCVRegisterInfo.cpp | 211 if (auto VLEN = ST.getRealVLen()) { in adjustReg() local
213 const int64_t VLENB = *VLEN / 8; in adjustReg()
433 if (auto VLEN = STI.getRealVLen()) { in lowerVSPILL() local
434 const int64_t VLENB = *VLEN / 8; in lowerVSPILL()
516 if (auto VLEN = STI.getRealVLen()) { in lowerVRELOAD() local
517 const int64_t VLENB = *VLEN / 8; in lowerVRELOAD()
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| H A D | RISCVInsertVSETVLI.cpp | 965 static unsigned computeVLMAX(unsigned VLEN, unsigned SEW, in computeVLMAX() argument
969 VLEN = VLEN / LMul; in computeVLMAX()
971 VLEN = VLEN * LMul; in computeVLMAX()
972 return VLEN/SEW; in computeVLMAX()
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| H A D | RISCVSchedSiFiveP800.td | 40 defvar VLEN = 128;
42 !eq(mx, "M1") : !div(VLEN, sew),
43 !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),
44 !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),
45 !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),
46 !eq(mx, "MF2") : !div(!div(VLEN, 2), sew),
47 !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),
48 !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),
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| H A D | RISCVFeatures.td | 1732 // Some vector hardware implementations do not process all VLEN bits in parallel
1737 "Vector unit DLEN(data path width) is half of VLEN">;
1788 "Prefer vsetvli over read vlenb CSR to calculate VLEN">;
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| H A D | RISCVRegisterInfo.td | 515 // The V vector extension requires that VLEN >= 128 and <= 65536.
517 // thus `vscale` can be defined as VLEN/64,
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| H A D | RISCVTargetTransformInfo.cpp | 2286 if (auto VLEN = ST->getRealVLen()) { in getVectorInstrCost() local
2288 unsigned M1Max = *VLEN / EltSize; in getVectorInstrCost()
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| H A D | RISCVISelDAGToDAG.cpp | 493 if (auto VLEN = Subtarget->getRealVLen()) in selectVSETVLI() local
494 if (*VLEN / RISCVVType::getSEWLMULRatio(SEW, VLMul) == C->getZExtValue()) in selectVSETVLI()
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| H A D | RISCVISelLowering.cpp | 5880 if (auto VLEN = Subtarget.getRealVLen(); in lowerVECTOR_SHUFFLE() local
5881 VLEN && VT.getSizeInBits().getKnownMinValue() % *VLEN == 0) in lowerVECTOR_SHUFFLE()
9990 if (auto VLEN = Subtarget.getRealVLen(); VLEN && ContainerVT.bitsGT(M1VT)) { in lowerINSERT_VECTOR_ELT() local
9992 unsigned ElemsPerVReg = *VLEN / ElemVT.getFixedSizeInBits(); in lowerINSERT_VECTOR_ELT()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGOpenMPRuntime.cpp | 10868 static void addAArch64VectorName(T VLEN, StringRef LMask, StringRef Prefix, in addAArch64VectorName() argument
10874 Out << Prefix << ISA << LMask << VLEN; in addAArch64VectorName()
11165 unsigned VLEN = VLENVal.getExtValue(); in emitDeclareSimdFunction() local
11168 emitAArch64DeclareSimdFunction(CGM, FD, VLEN, ParamAttrs, State, in emitDeclareSimdFunction()
11171 emitAArch64DeclareSimdFunction(CGM, FD, VLEN, ParamAttrs, State, in emitDeclareSimdFunction()
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