| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1409 VECREDUCE_XOR, enumerator
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 537 case ISD::VECREDUCE_XOR: return "vecreduce_xor"; in getOperationName()
|
| H A D | LegalizeVectorOps.cpp | 484 case ISD::VECREDUCE_XOR: in LegalizeOp()
1096 case ISD::VECREDUCE_XOR: in Expand()
|
| H A D | LegalizeIntegerTypes.cpp | 286 case ISD::VECREDUCE_XOR: in PromoteIntegerResult()
2004 case ISD::VECREDUCE_XOR: in PromoteIntegerOperand()
2568 case ISD::VECREDUCE_XOR: in getExtendForIntVecReduction()
2613 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2614 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_XOR, InVT) && in PromoteIntOp_VECREDUCE()
2928 case ISD::VECREDUCE_XOR: in ExpandIntegerResult()
|
| H A D | LegalizeVectorTypes.cpp | 800 case ISD::VECREDUCE_XOR: in ScalarizeVectorOperand()
3229 case ISD::VECREDUCE_XOR: in SplitVectorOperand()
6440 case ISD::VECREDUCE_XOR: in WidenVectorOperand()
|
| H A D | LegalizeDAG.cpp | 1204 case ISD::VECREDUCE_XOR: in LegalizeOp()
4310 case ISD::VECREDUCE_XOR: in ExpandNode()
|
| H A D | SelectionDAG.cpp | 451 case ISD::VECREDUCE_XOR: in getVecReduceBaseOpcode()
6200 return getNode(ISD::VECREDUCE_XOR, DL, VT, N1); in getNode()
|
| H A D | SelectionDAGBuilder.cpp | 10745 Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1); in visitVectorReduce()
|
| H A D | DAGCombiner.cpp | 1981 case ISD::VECREDUCE_XOR: in visit()
9434 reassociateReduction(ISD::VECREDUCE_XOR, ISD::XOR, DL, VT, N0, N1)) in visitXOR()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 787 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1127 setTargetDAGCombine(ISD::VECREDUCE_XOR); in AArch64TargetLowering()
1312 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1317 setOperationAction(ISD::VECREDUCE_XOR, MVT::v2i64, Custom); in AArch64TargetLowering()
1464 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1525 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1738 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
2119 setOperationAction(ISD::VECREDUCE_XOR, VT, Default); in addTypeForFixedLengthSVE()
6955 case ISD::VECREDUCE_XOR: in LowerOperation()
15178 case ISD::VECREDUCE_XOR: in getVectorBitwiseReduce()
15277 Op.getOpcode() == ISD::VECREDUCE_XOR || in LowerVECREDUCE()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 723 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in RISCVTargetLowering()
771 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
1176 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
6783 case ISD::VECREDUCE_XOR: in LowerOperation()
9695 case ISD::VECREDUCE_XOR: in getRVVReductionOp()
9719 Op.getOpcode() == ISD::VECREDUCE_XOR || in lowerVectorMaskVecReduction()
9766 case ISD::VECREDUCE_XOR: in lowerVectorMaskVecReduction()
12883 case ISD::VECREDUCE_XOR: in ReplaceNodeResults()
12933 return ISD::VECREDUCE_XOR; in getVecReduceOpcode()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 351 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 313 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in addMVEVectorTypes()
10304 case ISD::VECREDUCE_XOR: BaseOpcode = ISD::XOR; break; in LowerVecReduce()
10663 case ISD::VECREDUCE_XOR: in LowerOperation()
|