| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1489 VECREDUCE_XOR, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 559 case ISD::VECREDUCE_XOR: return "vecreduce_xor"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 503 case ISD::VECREDUCE_XOR: in LegalizeOp()
1227 case ISD::VECREDUCE_XOR: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 306 case ISD::VECREDUCE_XOR: in PromoteIntegerResult()
2055 case ISD::VECREDUCE_XOR: in PromoteIntegerOperand()
2704 case ISD::VECREDUCE_XOR: in getExtendForIntVecReduction()
2749 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2750 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_XOR, InVT) && in PromoteIntOp_VECREDUCE()
3111 case ISD::VECREDUCE_XOR: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 813 case ISD::VECREDUCE_XOR: in ScalarizeVectorOperand()
3509 case ISD::VECREDUCE_XOR: in SplitVectorOperand()
6887 case ISD::VECREDUCE_XOR: in WidenVectorOperand()
7653 case ISD::VECREDUCE_XOR: in getExtendForIntVecReduction()
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| H A D | LegalizeDAG.cpp | 1234 case ISD::VECREDUCE_XOR: in LegalizeOp()
4448 case ISD::VECREDUCE_XOR: in ExpandNode()
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| H A D | SelectionDAG.cpp | 463 case ISD::VECREDUCE_XOR: in getVecReduceBaseOpcode()
6614 return getNode(ISD::VECREDUCE_XOR, DL, VT, N1); in getNode()
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| H A D | DAGCombiner.cpp | 2050 case ISD::VECREDUCE_XOR: in visit()
9888 reassociateReduction(ISD::VECREDUCE_XOR, ISD::XOR, DL, VT, N0, N1)) in visitXOR()
27857 Opcode == ISD::VECREDUCE_XOR) && in visitVECREDUCE()
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| H A D | SelectionDAGBuilder.cpp | 10907 Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1); in visitVectorReduce()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 639 vector_reduce_xor, VECREDUCE_XOR)
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 884 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1172 setTargetDAGCombine(ISD::VECREDUCE_XOR); in AArch64TargetLowering()
1367 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1372 setOperationAction(ISD::VECREDUCE_XOR, MVT::v2i64, Custom); in AArch64TargetLowering()
1556 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1616 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1867 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
2356 setOperationAction(ISD::VECREDUCE_XOR, VT, Default); in addTypeForFixedLengthSVE()
7423 case ISD::VECREDUCE_XOR: in LowerOperation()
15951 case ISD::VECREDUCE_XOR: in getVectorBitwiseReduce()
16075 Op.getOpcode() == ISD::VECREDUCE_XOR || in LowerVECREDUCE()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 766 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in RISCVTargetLowering()
818 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
1290 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
7759 case ISD::VECREDUCE_XOR: in LowerOperation()
11087 case ISD::VECREDUCE_XOR: in getRVVReductionOp()
11111 Op.getOpcode() == ISD::VECREDUCE_XOR || in lowerVectorMaskVecReduction()
11156 case ISD::VECREDUCE_XOR: in lowerVectorMaskVecReduction()
14772 case ISD::VECREDUCE_XOR: in ReplaceNodeResults()
14822 return ISD::VECREDUCE_XOR; in getVecReduceOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 349 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 318 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in addMVEVectorTypes()
10353 case ISD::VECREDUCE_XOR: BaseOpcode = ISD::XOR; break; in LowerVecReduce()
10724 case ISD::VECREDUCE_XOR: in LowerOperation()
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