Lines Matching refs:VECREDUCE_XOR
1127 setTargetDAGCombine(ISD::VECREDUCE_XOR); in AArch64TargetLowering()
1312 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1317 setOperationAction(ISD::VECREDUCE_XOR, MVT::v2i64, Custom); in AArch64TargetLowering()
1464 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1525 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1738 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
2119 setOperationAction(ISD::VECREDUCE_XOR, VT, Default); in addTypeForFixedLengthSVE()
6955 case ISD::VECREDUCE_XOR: in LowerOperation()
15178 case ISD::VECREDUCE_XOR: in getVectorBitwiseReduce()
15277 Op.getOpcode() == ISD::VECREDUCE_XOR || in LowerVECREDUCE()
15303 case ISD::VECREDUCE_XOR: in LowerVECREDUCE()
15325 case ISD::VECREDUCE_XOR: in LowerVECREDUCE()
25264 case ISD::VECREDUCE_XOR: in PerformDAGCombine()
27695 case ISD::VECREDUCE_XOR: { in LowerPredReductionToSVE()