| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1407 VECREDUCE_AND, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 535 case ISD::VECREDUCE_AND: return "vecreduce_and"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 482 case ISD::VECREDUCE_AND: in LegalizeOp()
1094 case ISD::VECREDUCE_AND: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 284 case ISD::VECREDUCE_AND: in PromoteIntegerResult()
2002 case ISD::VECREDUCE_AND: in PromoteIntegerOperand()
2566 case ISD::VECREDUCE_AND: in getExtendForIntVecReduction()
2639 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2640 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_AND, InVT) && in PromoteIntOp_VECREDUCE()
2926 case ISD::VECREDUCE_AND: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 798 case ISD::VECREDUCE_AND: in ScalarizeVectorOperand()
3227 case ISD::VECREDUCE_AND: in SplitVectorOperand()
6438 case ISD::VECREDUCE_AND: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1202 case ISD::VECREDUCE_AND: in LegalizeOp()
4308 case ISD::VECREDUCE_AND: in ExpandNode()
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| H A D | DAGCombiner.cpp | 1979 case ISD::VECREDUCE_AND: in visit()
7027 reassociateReduction(ISD::VECREDUCE_AND, ISD::AND, DL, VT, N0, N1)) in visitAND()
26731 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
26732 unsigned NewOpcode = Opcode == ISD::VECREDUCE_AND in visitVECREDUCE()
26748 (Opcode == ISD::VECREDUCE_AND && in visitVECREDUCE()
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| H A D | SelectionDAG.cpp | 445 case ISD::VECREDUCE_AND: in getVecReduceBaseOpcode()
6210 return getNode(ISD::VECREDUCE_AND, DL, VT, N1); in getNode()
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| H A D | SelectionDAGBuilder.cpp | 10739 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1); in visitVectorReduce()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 786 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1125 setTargetDAGCombine(ISD::VECREDUCE_AND); in AArch64TargetLowering()
1310 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1315 setOperationAction(ISD::VECREDUCE_AND, MVT::v2i64, Custom); in AArch64TargetLowering()
1462 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1523 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1736 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
2107 setOperationAction(ISD::VECREDUCE_AND, VT, Default); in addTypeForFixedLengthSVE()
6953 case ISD::VECREDUCE_AND: in LowerOperation()
15172 case ISD::VECREDUCE_AND: in getVectorBitwiseReduce()
15275 Op.getOpcode() == ISD::VECREDUCE_AND || in LowerVECREDUCE()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 722 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
771 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
1176 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
6781 case ISD::VECREDUCE_AND: in LowerOperation()
9689 case ISD::VECREDUCE_AND: in getRVVReductionOp()
9717 assert((Op.getOpcode() == ISD::VECREDUCE_AND || in lowerVectorMaskVecReduction()
9749 case ISD::VECREDUCE_AND: in lowerVectorMaskVecReduction()
12881 case ISD::VECREDUCE_AND: in ReplaceNodeResults()
12929 return ISD::VECREDUCE_AND; in getVecReduceOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 350 ISD::VECREDUCE_ADD, ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, in initVPUActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 311 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in addMVEVectorTypes()
10302 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break; in LowerVecReduce()
10661 case ISD::VECREDUCE_AND: in LowerOperation()
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