| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1487 VECREDUCE_AND, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 557 case ISD::VECREDUCE_AND: return "vecreduce_and"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 501 case ISD::VECREDUCE_AND: in LegalizeOp()
1225 case ISD::VECREDUCE_AND: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 304 case ISD::VECREDUCE_AND: in PromoteIntegerResult()
2053 case ISD::VECREDUCE_AND: in PromoteIntegerOperand()
2702 case ISD::VECREDUCE_AND: in getExtendForIntVecReduction()
2775 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2776 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_AND, InVT) && in PromoteIntOp_VECREDUCE()
3109 case ISD::VECREDUCE_AND: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 811 case ISD::VECREDUCE_AND: in ScalarizeVectorOperand()
3507 case ISD::VECREDUCE_AND: in SplitVectorOperand()
6885 case ISD::VECREDUCE_AND: in WidenVectorOperand()
7651 case ISD::VECREDUCE_AND: in getExtendForIntVecReduction()
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| H A D | LegalizeDAG.cpp | 1232 case ISD::VECREDUCE_AND: in LegalizeOp()
4446 case ISD::VECREDUCE_AND: in ExpandNode()
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| H A D | DAGCombiner.cpp | 2048 case ISD::VECREDUCE_AND: in visit()
7449 reassociateReduction(ISD::VECREDUCE_AND, ISD::AND, DL, VT, N0, N1)) in visitAND()
27832 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
27833 unsigned NewOpcode = Opcode == ISD::VECREDUCE_AND in visitVECREDUCE()
27849 (Opcode == ISD::VECREDUCE_AND && in visitVECREDUCE()
27856 if ((Opcode == ISD::VECREDUCE_OR || Opcode == ISD::VECREDUCE_AND || in visitVECREDUCE()
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| H A D | SelectionDAG.cpp | 457 case ISD::VECREDUCE_AND: in getVecReduceBaseOpcode()
6624 return getNode(ISD::VECREDUCE_AND, DL, VT, N1); in getNode()
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| H A D | SelectionDAGBuilder.cpp | 10901 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1); in visitVectorReduce()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 631 vector_reduce_and, VECREDUCE_AND)
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 883 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1170 setTargetDAGCombine(ISD::VECREDUCE_AND); in AArch64TargetLowering()
1365 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1370 setOperationAction(ISD::VECREDUCE_AND, MVT::v2i64, Custom); in AArch64TargetLowering()
1554 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1614 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1865 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
2344 setOperationAction(ISD::VECREDUCE_AND, VT, Default); in addTypeForFixedLengthSVE()
7421 case ISD::VECREDUCE_AND: in LowerOperation()
15945 case ISD::VECREDUCE_AND: in getVectorBitwiseReduce()
16073 Op.getOpcode() == ISD::VECREDUCE_AND || in LowerVECREDUCE()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 765 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
818 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
1290 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
7757 case ISD::VECREDUCE_AND: in LowerOperation()
11081 case ISD::VECREDUCE_AND: in getRVVReductionOp()
11109 assert((Op.getOpcode() == ISD::VECREDUCE_AND || in lowerVectorMaskVecReduction()
11138 case ISD::VECREDUCE_AND: in lowerVectorMaskVecReduction()
14770 case ISD::VECREDUCE_AND: in ReplaceNodeResults()
14818 return ISD::VECREDUCE_AND; in getVecReduceOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 348 ISD::VECREDUCE_ADD, ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, in initVPUActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 316 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in addMVEVectorTypes()
10351 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break; in LowerVecReduce()
10722 case ISD::VECREDUCE_AND: in LowerOperation()
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