Lines Matching refs:VECREDUCE_AND
1125 setTargetDAGCombine(ISD::VECREDUCE_AND); in AArch64TargetLowering()
1310 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1315 setOperationAction(ISD::VECREDUCE_AND, MVT::v2i64, Custom); in AArch64TargetLowering()
1462 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1523 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1736 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
2107 setOperationAction(ISD::VECREDUCE_AND, VT, Default); in addTypeForFixedLengthSVE()
6953 case ISD::VECREDUCE_AND: in LowerOperation()
15172 case ISD::VECREDUCE_AND: in getVectorBitwiseReduce()
15275 Op.getOpcode() == ISD::VECREDUCE_AND || in LowerVECREDUCE()
15291 case ISD::VECREDUCE_AND: in LowerVECREDUCE()
15323 case ISD::VECREDUCE_AND: in LowerVECREDUCE()
23935 LHS = DAG.getNode(IsNull ? ISD::VECREDUCE_OR : ISD::VECREDUCE_AND, in performSETCCCombine()
25262 case ISD::VECREDUCE_AND: in PerformDAGCombine()
27691 case ISD::VECREDUCE_AND: { in LowerPredReductionToSVE()