| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1405 VECREDUCE_ADD, enumerator
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 628 return Opc != ISD::VECREDUCE_ADD; in shouldReassociateReduction()
|
| H A D | ARMISelLowering.cpp | 305 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal); in addMVEVectorTypes()
1037 ISD::INTRINSIC_VOID, ISD::VECREDUCE_ADD, ISD::ADD, ISD::BITCAST}); in ARMTargetLowering()
13574 case ISD::VECREDUCE_ADD: in TryDistrubutionADDVecReduce()
17100 assert(N->getOpcode() == ISD::VECREDUCE_ADD); in PerformVECREDUCE_ADDCombine()
17109 SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0)); in PerformVECREDUCE_ADDCombine()
17110 SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1)); in PerformVECREDUCE_ADDCombine()
17345 return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext); in PerformVECREDUCE_ADDCombine()
18972 case ISD::VECREDUCE_ADD: in PerformDAGCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 533 case ISD::VECREDUCE_ADD: return "vecreduce_add"; in getOperationName()
|
| H A D | LegalizeVectorOps.cpp | 480 case ISD::VECREDUCE_ADD: in LegalizeOp()
1092 case ISD::VECREDUCE_ADD: in Expand()
|
| H A D | LegalizeIntegerTypes.cpp | 282 case ISD::VECREDUCE_ADD: in PromoteIntegerResult()
2000 case ISD::VECREDUCE_ADD: in PromoteIntegerOperand()
2564 case ISD::VECREDUCE_ADD: in getExtendForIntVecReduction()
2615 TLI.isOperationLegalOrCustom(ISD::VECREDUCE_ADD, InVT)) in PromoteIntOp_VECREDUCE()
2616 Opcode = ISD::VECREDUCE_ADD; in PromoteIntOp_VECREDUCE()
2924 case ISD::VECREDUCE_ADD: in ExpandIntegerResult()
|
| H A D | LegalizeVectorTypes.cpp | 796 case ISD::VECREDUCE_ADD: in ScalarizeVectorOperand()
3225 case ISD::VECREDUCE_ADD: in SplitVectorOperand()
6436 case ISD::VECREDUCE_ADD: in WidenVectorOperand()
|
| H A D | LegalizeDAG.cpp | 1200 case ISD::VECREDUCE_ADD: in LegalizeOp()
4306 case ISD::VECREDUCE_ADD: in ExpandNode()
|
| H A D | SelectionDAG.cpp | 439 case ISD::VECREDUCE_ADD: in getVecReduceBaseOpcode()
6198 case ISD::VECREDUCE_ADD: in getNode()
|
| H A D | SelectionDAGBuilder.cpp | 10733 Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1); in visitVectorReduce()
|
| H A D | TargetLowering.cpp | 11485 Popcount = DAG.getNode(ISD::VECREDUCE_ADD, DL, ScalarVT, Popcount); in expandVECTOR_COMPRESS()
|
| H A D | DAGCombiner.cpp | 1977 case ISD::VECREDUCE_ADD: in visit()
2750 reassociateReduction(ISD::VECREDUCE_ADD, ISD::ADD, DL, VT, N0, N1)) in visitADDLike()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1115 ISD::VECREDUCE_ADD, ISD::STEP_VECTOR}); in AArch64TargetLowering()
1305 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in AArch64TargetLowering()
1314 setOperationAction(ISD::VECREDUCE_ADD, MVT::v2i64, Custom); in AArch64TargetLowering()
1461 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in AArch64TargetLowering()
2106 setOperationAction(ISD::VECREDUCE_ADD, VT, Default); in addTypeForFixedLengthSVE()
6952 case ISD::VECREDUCE_ADD: in LowerOperation()
15225 Result = DAG.getNode(ISD::VECREDUCE_ADD, DL, ExtendedVT, Extended); in getVectorBitwiseReduce()
15279 (Op.getOpcode() != ISD::VECREDUCE_ADD && in LowerVECREDUCE()
15289 case ISD::VECREDUCE_ADD: in LowerVECREDUCE()
15328 case ISD::VECREDUCE_ADD: in LowerVECREDUCE()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 785 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, in initActions()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 350 ISD::VECREDUCE_ADD, ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, in initVPUActions()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 490 def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 722 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
1260 setOperationAction({ISD::VECREDUCE_ADD, ISD::VECREDUCE_SMAX, in RISCVTargetLowering()
6775 case ISD::VECREDUCE_ADD: in LowerOperation()
9674 case ISD::VECREDUCE_ADD: in getRVVReductionOp()
12880 case ISD::VECREDUCE_ADD: in ReplaceNodeResults()
12919 return ISD::VECREDUCE_ADD; in getVecReduceOpcode()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 458 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in SystemZTargetLowering()
6174 case ISD::VECREDUCE_ADD: in LowerOperation()
|