Lines Matching refs:VECREDUCE_ADD
1115 ISD::VECREDUCE_ADD, ISD::STEP_VECTOR}); in AArch64TargetLowering()
1305 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in AArch64TargetLowering()
1314 setOperationAction(ISD::VECREDUCE_ADD, MVT::v2i64, Custom); in AArch64TargetLowering()
1461 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in AArch64TargetLowering()
2106 setOperationAction(ISD::VECREDUCE_ADD, VT, Default); in addTypeForFixedLengthSVE()
6952 case ISD::VECREDUCE_ADD: in LowerOperation()
15225 Result = DAG.getNode(ISD::VECREDUCE_ADD, DL, ExtendedVT, Extended); in getVectorBitwiseReduce()
15279 (Op.getOpcode() != ISD::VECREDUCE_ADD && in LowerVECREDUCE()
15289 case ISD::VECREDUCE_ADD: in LowerVECREDUCE()
15328 case ISD::VECREDUCE_ADD: in LowerVECREDUCE()
17714 return DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i32, UADDLP); in performVecReduceAddCombineWithUADDLP()
17781 return DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0), Dot); in performVecReduceAddCombine()
17804 DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0), ConcatSDot16); in performVecReduceAddCombine()
17820 DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0), Dot); in performVecReduceAddCombine()
22810 return DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i16, Zipped); in vectorToScalarBitmask()
22824 return DAG.getNode(ISD::VECREDUCE_ADD, DL, ResultVT, RepresentativeBits); in vectorToScalarBitmask()
25405 case ISD::VECREDUCE_ADD: in PerformDAGCombine()
26190 case ISD::VECREDUCE_ADD: in ReplaceNodeResults()