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Searched refs:VA (Results 1 – 25 of 158) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td292 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
293 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP,
294 [(set Ty:$VD, (IntID Ty:$VA, Ty:$VB))]>;
300 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
301 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP,
302 [(set OutTy:$VD, (IntID InTy:$VA, InTy:$VB))]>;
308 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
309 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP,
310 [(set OutTy:$VD, (IntID In1Ty:$VA, In2Ty:$VB))]>;
327 : VXForm_BX<xo, (outs vrrc:$VD), (ins vrrc:$VA),
[all …]
H A DPPCInstrP10.td374 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, vrrc:$VB),
375 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,
381 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, gprc:$VB),
382 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,
390 bits<5> VA;
397 let Inst{11-15} = VA;
1460 VXForm_1<207, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, gprc:$VB),
1461 "vinsw $VD, $VB, $VA", IIC_VecGeneral,
1463 (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>,
1466 VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB),
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp714 SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA, in Passv64i1ArgInRegs() argument
719 assert(VA.isRegLoc() && NextVA.isRegLoc() && in Passv64i1ArgInRegs()
730 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); in Passv64i1ArgInRegs()
760 CCValAssign &VA = RVLocs[I]; in LowerReturn() local
761 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
765 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg()); in LowerReturn()
771 if (VA.getLocInfo() == CCValAssign::SExt) in LowerReturn()
772 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
773 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerReturn()
774 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp120 const CCValAssign &VA) override { in assignValueToReg()
121 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
122 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
124 assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size"); in assignValueToReg()
125 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size"); in assignValueToReg()
127 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
134 const CCValAssign &VA) override { in assignValueToAddress()
135 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
146 const CCValAssign &VA = VAs[0]; in assignCustomValue() local
147 assert(VA.needsCustom() && "Value doesn't need custom handling"); in assignCustomValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp200 const CCValAssign &VA, const SDLoc &DL) { in convertValVTToLocVT() argument
201 EVT LocVT = VA.getLocVT(); in convertValVTToLocVT()
203 switch (VA.getLocInfo()) { in convertValVTToLocVT()
216 const CCValAssign &VA, const SDLoc &DL) { in convertLocVTToValVT() argument
217 switch (VA.getLocInfo()) { in convertLocVTToValVT()
223 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); in convertLocVTToValVT()
231 const CCValAssign &VA, const SDLoc &DL) { in unpackFromRegLoc() argument
234 EVT LocVT = VA.getLocVT(); in unpackFromRegLoc()
255 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
258 return convertLocVTToValVT(DAG, Val, VA, DL); in unpackFromRegLoc()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepIICHVX.td124 InstrItinData <tc_0390c1ca, /*SLOT01,LOAD,VA,VX_DV*/
156 InstrItinData <tc_0ec46cf9, /*SLOT0123,VA*/
184 InstrItinData <tc_191381c1, /*SLOT0,STORE,VA*/
195 InstrItinData <tc_1ba8a0cd, /*SLOT01,LOAD,VA*/
206 InstrItinData <tc_227864f7, /*SLOT0,STORE,VA,VX_DV*/
213 InstrItinData <tc_257f6f7c, /*SLOT0123,VA*/
258 InstrItinData <tc_3aacf4a8, /*SLOT0123,VA*/
285 InstrItinData <tc_3e2aaafc, /*SLOT0,STORE,VA*/
291 InstrItinData <tc_447d9895, /*SLOT0,STORE,VA*/
297 InstrItinData <tc_453fe68d, /*SLOT01,LOAD,VA*/
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dcs42l56.txt9 - VA-supply, VCP-supply, VLDO-supply : power supplies for the device,
31 0 = 0.5 x VA
32 1 = 0.6 x VA
33 2 = 0.7 x VA
34 3 = 0.8 x VA
35 4 = 0.83 x VA
36 5 = 0.91 x VA
62 VA-supply = <&reg_audio>;
H A Dcs42l52.txt30 0 = 0.5 x VA
31 1 = 0.6 x VA
32 2 = 0.7 x VA
33 3 = 0.8 x VA
34 4 = 0.83 x VA
35 5 = 0.91 x VA
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp302 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
306 switch (VA.getLocInfo()) { in LowerCall()
312 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
315 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
318 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
324 if (VA.isRegLoc()) { in LowerCall()
325 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
327 assert(VA.isMemLoc() && "Must be register or memory argument."); in LowerCall()
332 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall()
415 const CCValAssign &VA = RVLocs[i]; in lowerCallResult() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp282 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
283 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
287 if (VA.needsCustom()) { in LowerReturn_32()
288 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
299 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Glue); in LowerReturn_32()
301 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
302 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
303 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
306 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Glue); in LowerReturn_32()
310 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp39 const CCValAssign &VA) override;
42 const CCValAssign &VA) override;
52 const CCValAssign &VA) { in assignValueToReg() argument
54 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
61 const CCValAssign &VA) { in assignValueToAddress() argument
147 const CCValAssign &VA) { in assignValueToReg() argument
149 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
154 const CCValAssign &VA) { in assignValueToAddress() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp225 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
227 if (VA.isRegLoc()) { in LowerFormalArguments()
228 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
238 unsigned Register = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
244 if (VA.getLocInfo() != CCValAssign::Full) { in LowerFormalArguments()
246 if (VA.getLocInfo() == CCValAssign::SExt) in LowerFormalArguments()
248 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerFormalArguments()
252 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
253 ArgValue = DAG.getNode((VA.getValVT() == MVT::f32) ? ISD::BITCAST in LowerFormalArguments()
255 DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp764 CCValAssign &VA = ArgLocs[j]; in handleAssignments() local
765 assert(VA.getValNo() == i && "Location doesn't correspond to current arg"); in handleAssignments()
767 if (VA.needsCustom()) { in handleAssignments()
781 const MVT ValVT = VA.getValVT(); in handleAssignments()
782 const MVT LocVT = VA.getLocVT(); in handleAssignments()
807 if (VA.getLocInfo() == CCValAssign::Indirect) { in handleAssignments()
824 VA.getLocInfo() != CCValAssign::Indirect) { in handleAssignments()
833 assert((VA.getLocInfo() != CCValAssign::Indirect || Part == 0) && in handleAssignments()
839 CCValAssign &VA = ArgLocs[j + Idx]; in handleAssignments() local
854 if (VA.getLocInfo() == CCValAssign::Indirect && in handleAssignments()
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc7280-herobrine-villager-r1.dtsi22 "VA DMIC0", "vdd-micb",
23 "VA DMIC1", "vdd-micb",
24 "VA DMIC2", "vdd-micb",
25 "VA DMIC3", "vdd-micb",
H A Dsc7280-crd-r3.dts100 "VA DMIC0", "MIC BIAS1",
101 "VA DMIC1", "MIC BIAS1",
102 "VA DMIC2", "MIC BIAS3",
103 "VA DMIC3", "MIC BIAS3",
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp347 auto &VA = ArgLocs[I]; in LowerFormalArguments() local
349 if (VA.isRegLoc()) { in LowerFormalArguments()
351 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
366 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
371 if (VA.getLocInfo() == CCValAssign::SExt) in LowerFormalArguments()
373 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
374 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerFormalArguments()
376 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
378 if (VA.getLocInfo() != CCValAssign::Full) in LowerFormalArguments()
379 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp42 const CCValAssign &VA) override;
60 const CCValAssign &VA) override { in assignValueToReg()
62 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
68 const CCValAssign &VA) override { in assignValueToAddress()
70 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
151 const CCValAssign &VA) { in assignValueToReg() argument
154 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
159 const CCValAssign &VA) { in assignValueToAddress() argument
184 const CCValAssign &VA) { in assignValueToReg() argument
H A DM68kCallLowering.h56 const CCValAssign &VA) override;
60 const CCValAssign &VA) override;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp76 static LLT getStackValueStoreTypeHack(const CCValAssign &VA) { in getStackValueStoreTypeHack() argument
77 const MVT ValVT = VA.getValVT(); in getStackValueStoreTypeHack()
79 : LLT(VA.getLocVT()); in getStackValueStoreTypeHack()
157 LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, in getStackValueStoreType()
162 return CallLowering::ValueHandler::getStackValueStoreType(DL, VA, Flags); in getStackValueStoreType()
163 return getStackValueStoreTypeHack(VA); in getStackValueStoreType()
167 const CCValAssign &VA) override { in assignValueToReg()
169 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
174 const CCValAssign &VA) override { in assignValueToAddress()
177 LLT ValTy(VA.getValVT()); in assignValueToAddress()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp300 const CCValAssign &VA) { in MatchingStackOffset() argument
369 if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) { in MatchingStackOffset()
433 const CCValAssign &VA, in LowerMemArgument() argument
442 if (VA.getLocInfo() == CCValAssign::Indirect) in LowerMemArgument()
443 ValVT = VA.getLocVT(); in LowerMemArgument()
445 ValVT = VA.getValVT(); in LowerMemArgument()
449 int Offset = VA.getLocMemOffset(); in LowerMemArgument()
450 if (VA.getValVT() == MVT::i8) { in LowerMemArgument()
452 } else if (VA.getValVT() == MVT::i16) { in LowerMemArgument()
481 if (VA.getLocInfo() == CCValAssign::ZExt) { in LowerMemArgument()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h275 const CCValAssign &VA,
282 const CCValAssign &VA) = 0;
289 const CCValAssign &VA) = 0;
297 const CCValAssign &VA) { in assignValueToAddress()
298 assignValueToAddress(Arg.Regs[ValRegIndex], Addr, MemTy, MPO, VA); in assignValueToAddress()
321 uint64_t MemSize, CCValAssign &VA) const;
325 Register extendRegister(Register ValReg, const CCValAssign &VA,
337 Register buildExtensionHint(const CCValAssign &VA, Register SrcReg,
342 const CCValAssign &VA) override;
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/PDB/Native/
H A DNativeSession.cpp221 bool NativeSession::addressForVA(uint64_t VA, uint32_t &Section, in addressForVA() argument
223 uint32_t RVA = VA - getLoadAddress(); in addressForVA()
294 uint64_t VA = getVAFromSectOffset(Section, Offset); in findLineNumbersBySectOffset() local
295 return Cache.findLineNumbersByVA(VA, Length); in findLineNumbersBySectOffset()
403 bool NativeSession::moduleIndexForVA(uint64_t VA, uint16_t &ModuleIndex) const { in moduleIndexForVA() argument
405 auto Iter = AddrToModuleIndex.find(VA); in moduleIndexForVA()
438 uint64_t VA = Session.getVAFromSectOffset(C.ISect, C.Off); in parseSectionContribs() local
439 uint64_t End = VA + C.Size; in parseSectionContribs()
443 if (!AddrMap.overlaps(VA, End)) in parseSectionContribs()
444 AddrMap.insert(VA, En in parseSectionContribs()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp90 const CCValAssign &VA) override { in assignValueToAddress()
92 uint64_t LocMemOffset = VA.getLocMemOffset(); in assignValueToAddress()
99 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
104 const CCValAssign &VA) override { in assignValueToReg()
107 if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) || in assignValueToReg()
108 ((VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::i64) && in assignValueToReg()
109 VA.getValVT() == MVT::f16)) { in assignValueToReg()
110 LLT DstTy = LLT::scalar(VA.getLocVT().getSizeInBits()); in assignValueToReg()
114 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
232 const CCValAssign &VA) override { in assignValueToAddress()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp454 for (const CCValAssign &VA : ArgLocs) { in LowerCCCArguments() local
455 if (VA.isRegLoc()) { in LowerCCCArguments()
457 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
461 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
467 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
469 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
470 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
472 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
474 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
475 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerCCCArguments()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp96 const CCValAssign &VA) override;
103 const CCValAssign &VA) override;
133 const CCValAssign &VA) { in assignValueToReg()
135 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
155 const CCValAssign &VA) { in assignValueToAddress() argument
203 const CCValAssign &VA) override;
211 const CCValAssign &VA) override;
222 const CCValAssign &VA) { in assignValueToReg()
223 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
246 const CCValAssign &VA) { in assignValueToAddress() argument
132 assignValueToReg(Register ValVReg,Register PhysReg,CCValAssign VA) assignValueToReg() argument
221 assignValueToReg(Register ValVReg,Register PhysReg,CCValAssign VA) assignValueToReg() argument
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