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Searched refs:V128 (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrSIMD.td50 defm "" : ARGUMENT<V128, v16i8>;
51 defm "" : ARGUMENT<V128, v8i16>;
52 defm "" : ARGUMENT<V128, v4i32>;
53 defm "" : ARGUMENT<V128, v2i64>;
54 defm "" : ARGUMENT<V128, v4f32>;
55 defm "" : ARGUMENT<V128, v2f64>;
56 defm "" : ARGUMENT<V128, v8f16>;
179 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
184 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
199 SIMD_I<(outs V128:$dst),
[all …]
H A DWebAssemblyRegisterInfo.td67 def V128 : WebAssemblyRegClass<[v8f16, v4f32, v2f64, v2i64, v4i32, v16i8,
H A DWebAssemblyAsmPrinter.cpp123 case wasm::ValType::V128: in getInvokeSig()
H A DWebAssemblyInstrInfo.td376 defm "" : LOCAL<V128, global_op32>, Requires<[HasSIMD128]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td5294 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
5300 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
5523 (f16 (extractelt (v8f16 V128:$Rm), (i64 0))),
5526 FPR16:$Rn, (f16 (EXTRACT_SUBREG V128:$Rm, hsub)), FPR16:$Ra)>;
5528 def : Pat<(f16 (node (f16 (extractelt (v8f16 V128:$Rn), (i64 0))),
5532 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), FPR16:$Rm, FPR16:$Ra)>;
5536 (f32 (extractelt (v4f32 V128:$Rm), (i64 0))),
5539 FPR32:$Rn, (EXTRACT_SUBREG V128:$Rm, ssub), FPR32:$Ra)>;
5541 def : Pat<(f32 (node (f32 (extractelt (v4f32 V128:$Rn), (i64 0))),
5545 (EXTRACT_SUBREG V128:$Rn, ssub), FPR32:$Rm, FPR32:$Ra)>;
[all …]
H A DAArch64InstrInfo.td1375 def : Pat<(v4bf16 (any_fpround (v4f32 V128:$Rn))),
1376 (EXTRACT_SUBREG (BFCVTN V128:$Rn), dsub)>;
1422 (AArch64duplane32 (v4i32 V128:$Rm),
1429 def v16i8 : BaseSIMDSUDOTIndex<1, ".4s", ".16b", ".4b", V128, v4i32, v16i8>;
1460 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))),
1461 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>;
1463 def : Pat<(v2i64 (int_aarch64_crypto_sha512su0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
1464 (SHA512SU0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
1476 : Pat<(xor (xor (VecTy V128:$Vn), (VecTy V128:$Vm)), (VecTy V128:$Va)),
1477 (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
[all …]
H A DAArch64InstrGISel.td333 (FCVTNv2i32 (SCVTFv2f64 V128:$src))>;
335 (FCVTNv2i32 (UCVTFv2f64 V128:$src))>;
342 (XTNv2i32 (FCVTZSv2f64 V128:$src))>;
344 (XTNv2i32 (FCVTZUv2f64 V128:$src))>;
379 def : PatIgnoreCopies<(i32 (sext (i8 (intOp (v16i8 V128:$Rn))))),
382 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
384 def : Pat<(i8 (intOp (v16i8 V128:$Rn))),
385 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn)>;
395 def : PatIgnoreCopies<(i32 (sext (i16 (intOp (v8i16 V128:$Rn))))),
398 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
[all …]
H A DAArch64RegisterInfo.td563 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
H A DSVEInstrFormats.td9862 : I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
10107 : I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
H A DAArch64SVEInstrInfo.td1956 def : Pat<(SVEContainerVT<VT>.Value (vector_insert_subvec undef, (VT V128:$src), (i64 0))),
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTypeUtilities.cpp27 wasm::ValType::V128) in parseType()
41 .Case("v128", WebAssembly::BlockType::V128) in parseBlockType()
112 return wasm::ValType::V128; in regClassToValType()
H A DWebAssemblyMCTypeUtilities.h32 V128 = unsigned(wasm::ValType::V128), enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp57 return wasm::ValType::V128; in toValType()
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DWasm.h262 V128 = WASM_TYPE_V128, enumerator
/freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DWasmYAML.cpp606 ECase(V128); in enumeration()