Lines Matching refs:V128
5294 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
5300 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
5523 (f16 (extractelt (v8f16 V128:$Rm), (i64 0))),
5526 FPR16:$Rn, (f16 (EXTRACT_SUBREG V128:$Rm, hsub)), FPR16:$Ra)>;
5528 def : Pat<(f16 (node (f16 (extractelt (v8f16 V128:$Rn), (i64 0))),
5532 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), FPR16:$Rm, FPR16:$Ra)>;
5536 (f32 (extractelt (v4f32 V128:$Rm), (i64 0))),
5539 FPR32:$Rn, (EXTRACT_SUBREG V128:$Rm, ssub), FPR32:$Ra)>;
5541 def : Pat<(f32 (node (f32 (extractelt (v4f32 V128:$Rn), (i64 0))),
5545 (EXTRACT_SUBREG V128:$Rn, ssub), FPR32:$Rm, FPR32:$Ra)>;
5548 (f64 (extractelt (v2f64 V128:$Rm), (i64 0))),
5551 FPR64:$Rn, (EXTRACT_SUBREG V128:$Rm, dsub), FPR64:$Ra)>;
5553 def : Pat<(f64 (node (f64 (extractelt (v2f64 V128:$Rn), (i64 0))),
5557 (EXTRACT_SUBREG V128:$Rn, dsub), FPR64:$Rm, FPR64:$Ra)>;
5820 Sched<[!if(!eq(regtype, V128), WriteVq, WriteVd)]>;
5826 def v16i8 : BaseSIMDThreeSameVectorPseudo<V128,
5827 [(set (v16i8 V128:$dst),
5828 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
5829 (v16i8 V128:$Rm)))]>;
5844 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
5845 (v8i16 V128:$RHS))),
5847 V128:$LHS, V128:$MHS, V128:$RHS)>;
5848 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
5849 (v4i32 V128:$RHS))),
5851 V128:$LHS, V128:$MHS, V128:$RHS)>;
5852 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
5853 (v2i64 V128:$RHS))),
5855 V128:$LHS, V128:$MHS, V128:$RHS)>;
5864 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
5866 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
5870 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
5872 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5876 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
5878 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5879 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b111, opc, V128,
5881 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5892 def : Pat<(v16i8 (OpNode V128:$LHS, V128:$RHS)),
5893 (!cast<Instruction>(inst#"v16i8") V128:$LHS, V128:$RHS)>;
5894 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
5895 (!cast<Instruction>(inst#"v8i16") V128:$LHS, V128:$RHS)>;
5896 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
5897 (!cast<Instruction>(inst#"v4i32") V128:$LHS, V128:$RHS)>;
5898 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
5899 (!cast<Instruction>(inst#"v2i64") V128:$LHS, V128:$RHS)>;
5908 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
5910 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
5914 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
5916 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
5920 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
5922 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
5931 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b001, opc, V128,
5933 [(set (v16i8 V128:$dst),
5934 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
5939 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b011, opc, V128,
5941 [(set (v8i16 V128:$dst),
5942 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5947 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b101, opc, V128,
5949 [(set (v4i32 V128:$dst),
5950 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5959 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
5961 [(set (v16i8 V128:$Rd),
5962 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
5973 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
5975 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
5980 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
5982 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
5983 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
5985 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
5996 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
5998 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
6003 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
6005 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
6006 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
6008 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
6019 def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128,
6021 [(set (v8f16 V128:$dst),
6022 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
6028 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0b01}, {0b11,opc}, V128,
6030 [(set (v4f32 V128:$dst),
6031 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
6032 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,0b11}, {0b11,opc}, V128,
6034 [(set (v2f64 V128:$dst),
6035 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
6045 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
6047 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
6051 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
6053 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6062 def v16i8 : BaseSIMDThreeSameVector<1, U, {size,1}, 0b00011, V128,
6064 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
6073 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
6074 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
6075 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
6076 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
6077 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
6078 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
6087 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, {size,1}, 0b00011, V128,
6089 [(set (v16i8 V128:$dst),
6090 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
6091 (v16i8 V128:$Rm)))]>;
6106 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
6107 (v8i16 V128:$RHS))),
6109 V128:$LHS, V128:$MHS, V128:$RHS)>;
6110 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
6111 (v4i32 V128:$RHS))),
6113 V128:$LHS, V128:$MHS, V128:$RHS)>;
6114 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
6115 (v2i64 V128:$RHS))),
6117 V128:$LHS, V128:$MHS, V128:$RHS)>;
6137 def v16i8 : BaseSIMDThreeSameVectorDot<1, U, 0b10, {0b001, Mixed}, asm, ".4s", ".16b", V128,
6162 def v8f16 : BaseSIMDThreeSameVectorFML<1, U, b13, size, asm, ".4s", ".4h", V128,
6168 V128, v8f16, v16i8, null_frag>;
6173 V128, v4f32, v16i8, null_frag>;
6208 def v16f8 : BaseSIMDThreeVectors<0b1, 0b0, 0b01, 0b1110, V128, V128, asm, ".16b", ".8h">;
6214 def v8f8 : BaseSIMDThreeVectors<0b0, 0b0, 0b00, 0b1110, V64, V128, asm, ".8b", ".4s">;
6216 V128, v16i8, v4f32, null_frag>;
6224 V128, v8f16, v16i8, null_frag>;
6231 V128, v4f32, v16i8, null_frag>;
6293 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
6295 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
6299 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
6301 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6305 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
6307 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6313 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
6332 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
6336 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
6340 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
6351 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
6353 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
6357 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
6359 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6363 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
6365 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6374 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128,
6376 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
6377 (v16i8 V128:$Rn)))]>;
6382 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
6384 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
6385 (v8i16 V128:$Rn)))]>;
6390 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
6392 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
6393 (v4i32 V128:$Rn)))]>;
6402 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128,
6404 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
6408 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
6410 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
6414 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
6416 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
6417 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, 0b00, V128,
6419 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
6427 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
6429 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
6433 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
6435 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6439 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
6441 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6442 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, 0b00, V128,
6444 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
6454 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, 0b00, V128,
6456 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
6466 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
6468 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
6472 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
6474 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
6487 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
6489 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
6494 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
6496 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
6497 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
6499 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
6515 def v4f32 : BaseSIMDTwoSameVector<1, U, 00, opc, 0b00, V128,
6517 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
6518 def v2f64 : BaseSIMDTwoSameVector<1, U, 01, opc, 0b00, V128,
6520 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
6533 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
6535 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6545 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
6547 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
6552 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
6554 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
6555 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
6557 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
6567 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
6569 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6574 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
6576 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6577 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
6579 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
6630 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
6632 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6633 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
6635 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
6637 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6638 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
6640 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
6642 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
6643 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
6646 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
6648 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6649 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
6651 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6652 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
6654 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6661 def v8f16 : BaseSIMDMixedTwoVector<0b0, 0b1, sz, 0b10111, V64, V128,
6663 def 2v8f16 : BaseSIMDMixedTwoVector<0b1, 0b1, sz, 0b10111, V128, V128,
6698 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, 0b00, opc, V128,
6704 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, 0b00, opc, V128,
6710 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, 0b00, opc, V128,
6713 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, 0b00, opc, V128,
6727 def v8i16rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b11, opc, V128,
6734 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, 0b00, opc, V128,
6737 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b00, opc, V128,
6746 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
6751 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
6753 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
6758 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
6763 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
6765 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
6813 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
6815 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
6817 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
6819 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
6824 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
6826 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
6828 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
6830 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
6836 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
6838 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
6839 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
6842 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
6844 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6910 V64, V128, V128,
6912 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
6914 V128, V128, V128,
6918 V64, V128, V128,
6920 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6922 V128, V128, V128,
6926 V64, V128, V128,
6928 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
6930 V128, V128, V128,
6937 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
6938 (v8i16 V128:$Rm))),
6941 V128:$Rn, V128:$Rm)>;
6942 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
6943 (v4i32 V128:$Rm))),
6946 V128:$Rn, V128:$Rm)>;
6947 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
6948 (v2i64 V128:$Rm))),
6951 V128:$Rn, V128:$Rm)>;
6957 V128, V64, V64,
6959 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
6961 V128, V128, V128,
6965 V128, V64, V64,
6967 [(set (v16i8 V128:$Rd), (OpNode (v1i64 V64:$Rn), (v1i64 V64:$Rm)))]>;
6969 V128, V128, V128,
6971 [(set (v16i8 V128:$Rd), (OpNode (extract_high_v2i64 (v2i64 V128:$Rn)),
6972 (extract_high_v2i64 (v2i64 V128:$Rm))))]>;
6975 def : Pat<(v8i16 (OpNode (v8i8 (extract_high_v16i8 (v16i8 V128:$Rn))),
6976 (v8i8 (extract_high_v16i8 (v16i8 V128:$Rm))))),
6977 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
6983 V128, V64, V64,
6985 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
6987 V128, V128, V128,
6989 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
6990 (extract_high_v8i16 (v8i16 V128:$Rm))))]>;
6992 V128, V64, V64,
6994 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
6996 V128, V128, V128,
6998 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
6999 (extract_high_v4i32 (v4i32 V128:$Rm))))]>;
7005 V128, V64, V64,
7007 [(set (v8i16 V128:$Rd),
7010 V128, V128, V128,
7012 [(set (v8i16 V128:$Rd),
7013 (zext (v8i8 (OpNode (extract_high_v16i8 (v16i8 V128:$Rn)),
7014 (extract_high_v16i8 (v16i8 V128:$Rm))))))]>;
7016 V128, V64, V64,
7018 [(set (v4i32 V128:$Rd),
7021 V128, V128, V128,
7023 [(set (v4i32 V128:$Rd),
7024 (zext (v4i16 (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
7025 (extract_high_v8i16 (v8i16 V128:$Rm))))))]>;
7027 V128, V64, V64,
7029 [(set (v2i64 V128:$Rd),
7032 V128, V128, V128,
7034 [(set (v2i64 V128:$Rd),
7035 (zext (v2i32 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
7036 (extract_high_v4i32 (v4i32 V128:$Rm))))))]>;
7043 V128, V64, V64,
7045 [(set (v8i16 V128:$dst),
7046 (add (v8i16 V128:$Rd),
7049 V128, V128, V128,
7051 [(set (v8i16 V128:$dst),
7052 (add (v8i16 V128:$Rd),
7053 (zext (v8i8 (OpNode (extract_high_v16i8 (v16i8 V128:$Rn)),
7054 (extract_high_v16i8 (v16i8 V128:$Rm)))))))]>;
7056 V128, V64, V64,
7058 [(set (v4i32 V128:$dst),
7059 (add (v4i32 V128:$Rd),
7062 V128, V128, V128,
7064 [(set (v4i32 V128:$dst),
7065 (add (v4i32 V128:$Rd),
7066 (zext (v4i16 (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
7067 (extract_high_v8i16 (v8i16 V128:$Rm)))))))]>;
7069 V128, V64, V64,
7071 [(set (v2i64 V128:$dst),
7072 (add (v2i64 V128:$Rd),
7075 V128, V128, V128,
7077 [(set (v2i64 V128:$dst),
7078 (add (v2i64 V128:$Rd),
7079 (zext (v2i32 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
7080 (extract_high_v4i32 (v4i32 V128:$Rm)))))))]>;
7086 V128, V64, V64,
7088 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
7090 V128, V128, V128,
7092 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 (v16i8 V128:$Rn)),
7093 (extract_high_v16i8 (v16i8 V128:$Rm))))]>;
7095 V128, V64, V64,
7097 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
7099 V128, V128, V128,
7101 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
7102 (extract_high_v8i16 (v8i16 V128:$Rm))))]>;
7104 V128, V64, V64,
7106 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
7108 V128, V128, V128,
7110 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
7111 (extract_high_v4i32 (v4i32 V128:$Rm))))]>;
7118 V128, V64, V64,
7120 [(set (v8i16 V128:$dst),
7121 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
7123 V128, V128, V128,
7125 [(set (v8i16 V128:$dst),
7126 (OpNode (v8i16 V128:$Rd),
7127 (extract_high_v16i8 (v16i8 V128:$Rn)),
7128 (extract_high_v16i8 (v16i8 V128:$Rm))))]>;
7130 V128, V64, V64,
7132 [(set (v4i32 V128:$dst),
7133 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
7135 V128, V128, V128,
7137 [(set (v4i32 V128:$dst),
7138 (OpNode (v4i32 V128:$Rd),
7139 (extract_high_v8i16 (v8i16 V128:$Rn)),
7140 (extract_high_v8i16 (v8i16 V128:$Rm))))]>;
7142 V128, V64, V64,
7144 [(set (v2i64 V128:$dst),
7145 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
7147 V128, V128, V128,
7149 [(set (v2i64 V128:$dst),
7150 (OpNode (v2i64 V128:$Rd),
7151 (extract_high_v4i32 (v4i32 V128:$Rn)),
7152 (extract_high_v4i32 (v4i32 V128:$Rm))))]>;
7158 V128, V64, V64,
7160 [(set (v4i32 V128:$dst),
7161 (Accum (v4i32 V128:$Rd),
7165 V128, V128, V128,
7167 [(set (v4i32 V128:$dst),
7168 (Accum (v4i32 V128:$Rd),
7169 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 (v8i16 V128:$Rn)),
7170 (extract_high_v8i16 (v8i16 V128:$Rm))))))]>;
7172 V128, V64, V64,
7174 [(set (v2i64 V128:$dst),
7175 (Accum (v2i64 V128:$Rd),
7179 V128, V128, V128,
7181 [(set (v2i64 V128:$dst),
7182 (Accum (v2i64 V128:$Rd),
7183 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 (v4i32 V128:$Rn)),
7184 (extract_high_v4i32 (v4i32 V128:$Rm))))))]>;
7190 V128, V128, V64,
7192 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
7194 V128, V128, V128,
7196 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7197 (extract_high_v16i8 (v16i8 V128:$Rm))))]>;
7199 V128, V128, V64,
7201 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
7203 V128, V128, V128,
7205 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7206 (extract_high_v8i16 (v8i16 V128:$Rm))))]>;
7208 V128, V128, V64,
7210 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
7212 V128, V128, V128,
7214 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7215 (extract_high_v4i32 (v4i32 V128:$Rm))))]>;
7250 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
7263 Sched<[!if(!eq(regtype, V128), WriteVq, WriteVd)]> {
7284 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
7288 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
7292 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
7294 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
7301 def : Pat<(v8f16 (OpNode V128:$Rn, V128:$Rm)),
7302 (!cast<Instruction>(NAME#"v8i16") V128:$Rn, V128:$Rm)>;
7303 def : Pat<(v8bf16 (OpNode V128:$Rn, V128:$Rm)),
7304 (!cast<Instruction>(NAME#"v8i16") V128:$Rn, V128:$Rm)>;
7307 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
7308 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
7309 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
7310 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
7696 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
7708 def v2i64p : BaseSIMDPairwiseScalar<1, {S,1}, opc, FPR64Op, V128,
7741 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
7745 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
7747 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
7754 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
7758 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
7760 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
7771 def v8i16v : BaseSIMDAcrossLanes<1, 0, {sz1, 0}, opcode, FPR16, V128,
7773 [(set (f16 FPR16:$Rd), (intOp (v8f16 V128:$Rn)))]>;
7775 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
7777 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
7816 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
7820 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
7825 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
7861 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
7873 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
7879 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
7981 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
7982 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
7986 [(set V128:$dst,
7987 (vector_insert (vectype V128:$Rd), regtype:$Rn, (i64 idxtype:$idx)))]> {
7993 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
7994 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
7998 [(set V128:$dst,
8000 (vectype V128:$Rd),
8001 (elttype (vector_extract (vectype V128:$Rn), (i64 idxtype:$idx2))),
8008 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
8013 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
8152 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
8154 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
8156 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
8158 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
8175 V128, VecListOne128>;
8178 V128, VecListTwo128>;
8181 V128, VecListThree128>;
8184 V128, VecListFour128>;
8196 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
8198 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
8200 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
8202 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
8219 V128, VecListOne128>;
8222 V128, VecListTwo128>;
8225 V128, VecListThree128>;
8228 V128, VecListFour128>;
8259 …def v16f8 : BaseSIMDTableLookupIndexed<0b1, {0b10,?,?,0b1}, V128, VecListOne16b, VectorIndexS, asm…
8263 …def v8f16 : BaseSIMDTableLookupIndexed<0b1, {0b11,?,?,?}, V128, VecListOne8h, VectorIndexH, asm, "…
8270 …def v16f8 : BaseSIMDTableLookupIndexed<0b1, {0b01,?,0b10}, V128, VecListOne16b, VectorIndexD, asm,…
8274 …def v8f16 : BaseSIMDTableLookupIndexed<0b1, {0b01,?,?,0b1}, V128, VecListTwo8h, VectorIndexS, asm,…
8306 def i8 : BaseSIMDScalarDUP<FPR8, V128, asm, ".b", VectorIndexB> {
8311 def i16 : BaseSIMDScalarDUP<FPR16, V128, asm, ".h", VectorIndexH> {
8316 def i32 : BaseSIMDScalarDUP<FPR32, V128, asm, ".s", VectorIndexS> {
8321 def i64 : BaseSIMDScalarDUP<FPR64, V128, asm, ".d", VectorIndexD> {
8327 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
8329 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
8334 FPR8, V128, VectorIndexB>;
8337 FPR16, V128, VectorIndexH>;
8340 FPR32, V128, VectorIndexS>;
8343 FPR64, V128, VectorIndexD>;
8447 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
8452 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
8464 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
8466 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
8475 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
8477 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
8595 def v8bf16 : BaseSIMDThreeSameVectorBFDot<1, U, asm, ".4s", ".8h", V128,
8606 RegType, RegType, V128, VectorIndexS,
8613 (AArch64duplane32 (v4f32 V128:$Rm),
8626 ".2h", V128, v4f32, v8bf16>;
8631 : BaseSIMDThreeSameVectorTied<Q, 0b1, 0b110, 0b11111, V128, asm, ".4s",
8632 [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
8633 (v8bf16 V128:$Rn),
8634 (v8bf16 V128:$Rm)))]> {
8640 : I<(outs V128:$dst),
8641 (ins V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx), asm,
8643 [(set (v4f32 V128:$dst),
8644 (v4f32 (OpNode (v4f32 V128:$Rd),
8645 (v8bf16 V128:$Rn),
8669 V128, asm, ".4s",
8670 [(set (v4f32 V128:$dst),
8671 (int_aarch64_neon_bfmmla (v4f32 V128:$Rd),
8672 (v8bf16 V128:$Rn),
8673 (v8bf16 V128:$Rm)))]> {
8680 : BaseSIMDMixedTwoVector<0, 0, 0b10, 0b10110, V128, V128,
8682 [(set (v8bf16 V128:$Rd),
8683 (int_aarch64_neon_bfcvtn (v4f32 V128:$Rn)))]>;
8687 : BaseSIMDMixedTwoVectorTied<1, 0, 0b10, 0b10110, V128, V128,
8689 [(set (v8bf16 V128:$dst),
8690 (int_aarch64_neon_bfcvtn2 (v8bf16 V128:$Rd), (v4f32 V128:$Rn)))]>;
8722 V128, V128_0to7>;
8727 V128, V128_0to7>;
8735 : BaseSIMDThreeSameVectorTied<1, U, 0b100, {0b1010, B}, V128, asm, ".4s",
8736 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
8737 (v16i8 V128:$Rn),
8738 (v16i8 V128:$Rm)))]> {
8749 BaseSIMDIndexedTied<Q, U, 0b0, size, opc, RegType, RegType, V128,
8755 (AArch64duplane32 (v4i32 V128:$Rm),
8767 V128, v4i32, v16i8, OpNode>;
8775 V128, v4f32, v16i8, null_frag>;
8804 V128, V128_lo, v4f32, v8f16, OpNode>;
8814 V128, V128_lo, v8f16, v8i16, null_frag>;
8835 V128, V128,
8838 [(set (v8f16 V128:$Rd),
8839 (OpNode (v8f16 V128:$Rn),
8850 V128, VectorIndexS,
8854 (dup_v4f32 (v4f32 V128:$Rm), VectorIndexS:$idx)))]> {
8861 V128, V128,
8862 V128, VectorIndexS,
8864 [(set (v4f32 V128:$Rd),
8865 (OpNode (v4f32 V128:$Rn),
8866 (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
8873 V128, V128,
8874 V128, VectorIndexD,
8876 [(set (v2f64 V128:$Rd),
8877 (OpNode (v2f64 V128:$Rn),
8878 (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
8900 FPR32Op, FPR32Op, V128, VectorIndexS,
8904 (f32 (vector_extract (v4f32 V128:$Rm),
8912 FPR64Op, FPR64Op, V128, VectorIndexD,
8916 (f64 (vector_extract (v2f64 V128:$Rm),
8926 (f16 (vector_extract (v8f16 V128:$Rn), (i64 0))),
8927 (f16 (vector_extract (v8f16 V128:$Rm), VectorIndexH:$idx)))),
8929 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), V128:$Rm, VectorIndexH:$idx)>;
8934 (f32 (vector_extract (v4f32 V128:$Rn), (i64 0))),
8935 (f32 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx)))),
8937 (EXTRACT_SUBREG V128:$Rn, ssub), V128:$Rm, VectorIndexS:$idx)>;
8940 (f64 (vector_extract (v2f64 V128:$Rn), (i64 0))),
8941 (f64 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx)))),
8943 (EXTRACT_SUBREG V128:$Rn, dsub), V128:$Rm, VectorIndexD:$idx)>;
8950 def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
8954 V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>;
8955 def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
8957 (!cast<Instruction>(INST # "v8i16_indexed") V128:$Rd, V128:$Rn,
8978 (AArch64duplane32 (v4f32 V128:$Rm),
8981 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
8989 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
8990 (AArch64duplane32 (v4f32 V128:$Rm),
8993 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
8994 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
8996 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
9000 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
9001 (AArch64duplane64 (v2f64 V128:$Rm),
9004 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
9005 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
9007 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
9012 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
9014 V128:$Rm, VectorIndexS:$idx)>;
9018 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
9020 V128:$Rm, VectorIndexD:$idx)>;
9036 V128, V128,
9047 V128, VectorIndexS,
9055 V128, V128,
9056 V128, VectorIndexS,
9064 V128, V128,
9065 V128, VectorIndexD,
9084 FPR32Op, FPR32Op, V128, VectorIndexS,
9092 FPR64Op, FPR64Op, V128, VectorIndexD,
9117 (v8i16 V128:$Rn), (v4i16 V64_lo:$Rm),
9124 (v8i16 V128:$Rn), (v8i16 V128_lo:$Rm),
9137 (v2i32 V64:$Rn), (v4i32 V128:$Rm),
9143 (v4i32 V128:$Rn), (v2i32 V64:$Rm),
9150 (v4i32 V128:$Rn),
9151 (v4i32 V128:$Rm),
9173 V128, V128,
9176 [(set (v8i16 V128:$Rd),
9177 (OpNode (v8i16 V128:$Rn),
9187 V128, VectorIndexS,
9191 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9198 V128, V128,
9199 V128, VectorIndexS,
9201 [(set (v4i32 V128:$Rd),
9202 (OpNode (v4i32 V128:$Rn),
9203 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
9219 FPR32Op, FPR32Op, V128, VectorIndexS,
9223 (i32 (vector_extract (v4i32 V128:$Rm),
9247 V128, V128,
9250 [(set (v8i16 V128:$Rd),
9251 (OpNode (v8i16 V128:$Rn),
9261 V128, VectorIndexS,
9265 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9272 V128, V128,
9273 V128, VectorIndexS,
9275 [(set (v4i32 V128:$Rd),
9276 (OpNode (v4i32 V128:$Rn),
9277 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
9299 V128, V128,
9302 [(set (v8i16 V128:$dst),
9303 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
9313 V128, VectorIndexS,
9317 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9324 V128, V128,
9325 V128, VectorIndexS,
9327 [(set (v4i32 V128:$dst),
9328 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
9329 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
9339 V128, V64,
9342 [(set (v4i32 V128:$Rd),
9352 V128, V128,
9355 [(set (v4i32 V128:$Rd),
9356 (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
9366 V128, V64,
9367 V128, VectorIndexS,
9369 [(set (v2i64 V128:$Rd),
9371 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9378 V128, V128,
9379 V128, VectorIndexS,
9381 [(set (v2i64 V128:$Rd),
9382 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
9383 (extract_high_dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9399 FPR64Op, FPR32Op, V128, VectorIndexS,
9410 V128, V64,
9413 [(set (v4i32 V128:$dst),
9414 (Accum (v4i32 V128:$Rd),
9426 V128, V128,
9429 [(set (v4i32 V128:$dst),
9430 (Accum (v4i32 V128:$Rd),
9432 (extract_high_v8i16 (v8i16 V128:$Rn)),
9441 V128, V64,
9442 V128, VectorIndexS,
9444 [(set (v2i64 V128:$dst),
9445 (Accum (v2i64 V128:$Rd),
9448 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))))]> {
9455 V128, V128,
9456 V128, VectorIndexS,
9458 [(set (v2i64 V128:$dst),
9459 (Accum (v2i64 V128:$Rd),
9461 (extract_high_v4i32 (v4i32 V128:$Rn)),
9462 (extract_high_dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))))]> {
9503 FPR64Op, FPR32Op, V128, VectorIndexS,
9509 (i32 (vector_extract (v4i32 V128:$Rm),
9522 V128, V64,
9525 [(set (v4i32 V128:$Rd),
9535 V128, V128,
9538 [(set (v4i32 V128:$Rd),
9539 (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
9549 V128, V64,
9550 V128, VectorIndexS,
9552 [(set (v2i64 V128:$Rd),
9554 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9561 V128, V128,
9562 V128, VectorIndexS,
9564 [(set (v2i64 V128:$Rd),
9565 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
9566 (extract_high_dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9578 V128, V64,
9581 [(set (v4i32 V128:$dst),
9582 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
9591 V128, V128,
9594 [(set (v4i32 V128:$dst),
9595 (OpNode (v4i32 V128:$Rd),
9596 (extract_high_v8i16 (v8i16 V128:$Rn)),
9605 V128, V64,
9606 V128, VectorIndexS,
9608 [(set (v2i64 V128:$dst),
9609 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
9610 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9617 V128, V128,
9618 V128, VectorIndexS,
9620 [(set (v2i64 V128:$dst),
9621 (OpNode (v2i64 V128:$Rd),
9622 (extract_high_v4i32 (v4i32 V128:$Rn)),
9623 (extract_high_dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9874 V128, V128, vecshiftR16,
9876 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (i32 imm:$imm)))]> {
9890 V128, V128, vecshiftR32,
9892 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
9898 V128, V128, vecshiftR64,
9900 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
9918 V128, V128, vecshiftR16,
9920 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (i32 imm:$imm)))]> {
9935 V128, V128, vecshiftR32,
9937 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
9943 V128, V128, vecshiftR64,
9945 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
9954 V64, V128, vecshiftR16Narrow,
9956 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
9962 V128, V128, vecshiftR16Narrow,
9970 V64, V128, vecshiftR32Narrow,
9972 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
9978 V128, V128, vecshiftR32Narrow,
9986 V64, V128, vecshiftR64Narrow,
9988 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
9994 V128, V128, vecshiftR64Narrow,
10006 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
10010 V128:$Rn, vecshiftR16Narrow:$imm)>;
10011 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
10015 V128:$Rn, vecshiftR32Narrow:$imm)>;
10016 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
10020 V128:$Rn, vecshiftR64Narrow:$imm)>;
10035 V128, V128, vecshiftL8,
10037 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
10053 V128, V128, vecshiftL16,
10055 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
10071 V128, V128, vecshiftL32,
10073 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
10080 V128, V128, vecshiftL64,
10082 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
10101 V128, V128, vecshiftR8,
10103 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
10119 V128, V128, vecshiftR16,
10121 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
10137 V128, V128, vecshiftR32,
10139 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
10146 V128, V128, vecshiftR64,
10148 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
10168 V128, V128, vecshiftR8, asm, ".16b", ".16b",
10169 [(set (v16i8 V128:$dst),
10170 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
10186 V128, V128, vecshiftR16, asm, ".8h", ".8h",
10187 [(set (v8i16 V128:$dst),
10188 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
10204 V128, V128, vecshiftR32, asm, ".4s", ".4s",
10205 [(set (v4i32 V128:$dst),
10206 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
10213 V128, V128, vecshiftR64,
10214 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
10215 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
10235 V128, V128, vecshiftL8,
10237 [(set (v16i8 V128:$dst),
10238 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
10255 V128, V128, vecshiftL16,
10257 [(set (v8i16 V128:$dst),
10258 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
10275 V128, V128, vecshiftL32,
10277 [(set (v4i32 V128:$dst),
10278 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
10285 V128, V128, vecshiftL64,
10287 [(set (v2i64 V128:$dst),
10288 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
10298 V128, V64, vecshiftL8, asm, ".8h", ".8b",
10299 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
10305 V128, V128, vecshiftL8,
10307 [(set (v8i16 V128:$Rd),
10308 (OpNode (extract_high_v16i8 (v16i8 V128:$Rn)), vecshiftL8:$imm))]> {
10314 V128, V64, vecshiftL16, asm, ".4s", ".4h",
10315 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
10321 V128, V128, vecshiftL16,
10323 [(set (v4i32 V128:$Rd),
10324 (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)), vecshiftL16:$imm))]> {
10331 V128, V64, vecshiftL32, asm, ".2d", ".2s",
10332 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
10338 V128, V128, vecshiftL32,
10340 [(set (v2i64 V128:$Rd),
10341 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)), vecshiftL32:$imm))]> {
11214 def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
11215 [(set (v8i16 V128:$dst),
11216 (v8i16 (op (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
11220 def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s",
11221 [(set (v4i32 V128:$dst),
11222 (v4i32 (op (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
11241 V128, V128, V128_lo, VectorIndexH,
11243 [(set (v8i16 V128:$dst),
11244 (v8i16 (op (v8i16 V128:$Rd), (v8i16 V128:$Rn),
11254 V64, V64, V128, VectorIndexS,
11258 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
11265 V128, V128, V128, VectorIndexS,
11267 [(set (v4i32 V128:$dst),
11268 (v4i32 (op (v4i32 V128:$Rd), (v4i32 V128:$Rn),
11269 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
11287 FPR32Op, FPR32Op, V128, VectorIndexS,
11291 (i32 (vector_extract (v4i32 V128:$Rm),
11363 def v8f16 : BaseSIMDThreeSameVectorComplex<1, U, 0b01, opcode, V128, rottype,
11365 [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
11366 (v8f16 V128:$Rn),
11367 (v8f16 V128:$Rm),
11379 def v4f32 : BaseSIMDThreeSameVectorComplex<1, U, 0b10, opcode, V128, rottype,
11381 [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
11382 (v4f32 V128:$Rn),
11383 (v4f32 V128:$Rm),
11386 def v2f64 : BaseSIMDThreeSameVectorComplex<1, U, 0b11, opcode, V128, rottype,
11388 [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
11389 (v2f64 V128:$Rn),
11390 (v2f64 V128:$Rm),
11435 def v8f16 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b01, opcode, V128,
11437 [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
11438 (v8f16 V128:$Rn),
11439 (v8f16 V128:$Rm),
11451 def v4f32 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b10, opcode, V128,
11453 [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
11454 (v4f32 V128:$Rn),
11455 (v4f32 V128:$Rm),
11458 def v2f64 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b11, opcode, V128,
11460 [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
11461 (v2f64 V128:$Rn),
11462 (v2f64 V128:$Rm),
11511 V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h",
11519 V128, V128, V128, VectorIndexS, rottype, asm, ".8h",
11529 V128, V128, V128, VectorIndexD, rottype, asm, ".4s",
11557 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
11558 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
11561 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
11563 [(set (v16i8 V128:$dst),
11564 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
11587 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
11590 (v4i32 V128:$Rm)))]>;
11593 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
11594 (ins V128:$Rd, V128:$Rn, V128:$Rm),
11595 [(set (v4i32 V128:$dst),
11596 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
11597 (v4i32 V128:$Rm)))]>;
11601 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
11604 (v4i32 V128:$Rm)))]>;
11623 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
11624 (ins V128:$Rd, V128:$Rn),
11625 [(set (v4i32 V128:$dst),
11626 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
11644 : BaseCryptoV82<(outs V128:$Vdst), (ins V128:$Vd, V128:$Vn), asm, asmops,
11670 : CryptoRRR<op0, op1, (outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm,
11673 : CryptoRRR<op0, op1, (outs V128:$Vdst), (ins V128:$Vd, V128:$Vn, V128:$Vm), asm,
11676 : CryptoRRR<op0, op1, (outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm,
11679 : CryptoRRR<op0, op1, (outs V128:$Vdst), (ins V128:$Vd, V128:$Vn, V128:$Vm), asm,
11682 : CryptoRRR<op0, op1, (outs FPR128:$Vdst), (ins FPR128:$Vd, FPR128:$Vn, V128:$Vm),
11686 : BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm, V128:$Va), asm,
11706 : BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm, uimm6:$imm), asm,
11719 : BaseCryptoV82<(outs V128:$Vdst),
11720 (ins V128:$Vd, V128:$Vn, V128:$Vm, VectorIndexS:$imm),