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Searched refs:UseMI (Results 1 – 25 of 86) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp90 bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
103 bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
196 MachineInstr &UseMI = *NodeAddr<StmtNode *>(IA).Addr->getCode(); in canRemoveAddasl() local
200 MI.getParent() != UseMI.getParent()) in canRemoveAddasl()
203 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
205 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset || in canRemoveAddasl()
206 getBaseWithLongOffset(UseMI) < 0) in canRemoveAddasl()
210 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() && in canRemoveAddasl()
211 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg()) in canRemoveAddasl()
214 for (auto &Mo : UseMI.operands()) in canRemoveAddasl()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp145 MachineInstr *UseMI; member
153 : UseMI(MI), Def(Def), ShrinkOpcode(ShrinkOp), UseOpNo(OpNo), in FoldCandidate()
182 bool frameIndexMayFold(const MachineInstr &UseMI, int OpNo,
233 bool tryFoldRegSeqSplat(MachineInstr *UseMI, unsigned UseOpIdx,
237 bool tryToFoldACImm(const FoldableDef &OpToFold, MachineInstr *UseMI,
240 void foldOperand(FoldableDef OpToFold, MachineInstr *UseMI, int UseOpIdx,
339 bool SIFoldOperandsImpl::frameIndexMayFold(const MachineInstr &UseMI, int OpNo, in frameIndexMayFold() argument
344 const unsigned Opc = UseMI.getOpcode(); in frameIndexMayFold()
353 return UseMI.getOperand(OpNo == 1 ? 2 : 1).isImm() && in frameIndexMayFold()
354 MRI->hasOneNonDBGUse(UseMI.getOperand(OpNo).getReg()); in frameIndexMayFold()
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H A DSIOptimizeVGPRLiveRange.cpp221 for (auto &UseMI : MRI->use_nodbg_instructions(Reg)) { in findNonPHIUsesInBlock() local
222 if (UseMI.getParent() == MBB && !UseMI.isPHI()) in findNonPHIUsesInBlock()
223 Uses.push_back(&UseMI); in findNonPHIUsesInBlock()
312 auto *UseMI = I->getParent(); in collectCandidateRegisters() local
313 auto *UseMBB = UseMI->getParent(); in collectCandidateRegisters()
315 if (!UseMI->isPHI()) in collectCandidateRegisters()
318 auto *IncomingMBB = UseMI->getOperand(I.getOperandNo() + 1).getMBB(); in collectCandidateRegisters()
435 auto *UseMI = I->getParent(); in updateLiveRangeInThenRegion() local
436 if (UseMI->isPHI() && I->readsReg()) { in updateLiveRangeInThenRegion()
437 if (Blocks.contains(UseMI->getParent())) in updateLiveRangeInThenRegion()
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H A DSIFixSGPRCopies.cpp248 const auto *UseMI = MO.getParent(); in tryChangeVGPRtoSGPRinCopy() local
249 if (UseMI == &MI) in tryChangeVGPRtoSGPRinCopy()
251 if (MO.isDef() || UseMI->getParent() != MI.getParent() || in tryChangeVGPRtoSGPRinCopy()
252 UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END) in tryChangeVGPRtoSGPRinCopy()
256 if (OpIdx >= UseMI->getDesc().getNumOperands() || in tryChangeVGPRtoSGPRinCopy()
257 !TII->isOperandLegal(*UseMI, OpIdx, &Src)) in tryChangeVGPRtoSGPRinCopy()
821 const MachineInstr *UseMI = Use.getParent(); in processPHINode() local
822 AllAGPRUses &= (UseMI->isCopy() && in processPHINode()
823 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) || in processPHINode()
825 if (UseMI->isCopy() || UseMI->isRegSequence()) { in processPHINode()
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H A DGCNSchedStrategy.h449 MachineInstr *UseMI; member
457 RematInstruction(MachineInstr *UseMI) : UseMI(UseMI) {} in RematInstruction()
H A DAMDGPURegBankSelect.cpp154 for (auto &UseMI : make_early_inc_range(MRI.use_instructions(Reg))) { in reAssignRegBankOnDef() local
155 if (UseMI.isPreISelOpcode()) { in reAssignRegBankOnDef()
156 for (MachineOperand &Op : UseMI.operands()) { in reAssignRegBankOnDef()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp397 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { in foldIntoMemoryOps() local
398 switch (UseMI.getOpcode()) { in foldIntoMemoryOps()
400 LLVM_DEBUG(dbgs() << "Not a load or store instruction: " << UseMI); in foldIntoMemoryOps()
425 if (UseMI.getOperand(1).isFI()) in foldIntoMemoryOps()
428 if (DestReg == UseMI.getOperand(0).getReg()) in foldIntoMemoryOps()
430 assert(DestReg == UseMI.getOperand(1).getReg() && in foldIntoMemoryOps()
433 int64_t Offset = UseMI.getOperand(2).getImm(); in foldIntoMemoryOps()
444 I < UseMI.getNumOperands(); I += 1 + NumOps) { in foldIntoMemoryOps()
445 const MachineOperand &FlagsMO = UseMI.getOperand(I); in foldIntoMemoryOps()
458 const MachineOperand &MO = UseMI.getOperand(I + 1 + J); in foldIntoMemoryOps()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchMergeBaseOffset.cpp591 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { in foldIntoMemoryOps() local
592 switch (UseMI.getOpcode()) { in foldIntoMemoryOps()
594 LLVM_DEBUG(dbgs() << "Not a load or store instruction: " << UseMI); in foldIntoMemoryOps()
625 if (UseMI.getOperand(1).isFI()) in foldIntoMemoryOps()
628 if (DestReg == UseMI.getOperand(0).getReg()) in foldIntoMemoryOps()
630 assert(DestReg == UseMI.getOperand(1).getReg() && in foldIntoMemoryOps()
633 int64_t Offset = UseMI.getOperand(2).getImm(); in foldIntoMemoryOps()
647 I < UseMI.getNumOperands(); I += 1 + NumOps) { in foldIntoMemoryOps()
648 const MachineOperand &FlagsMO = UseMI.getOperand(I); in foldIntoMemoryOps()
661 const MachineOperand &MO = UseMI.getOperand(I + 1 + J); in foldIntoMemoryOps()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp205 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
217 if (UseMI && UseMI != MI) in foldAsLoad()
222 UseMI = MI; in foldAsLoad()
225 if (!DefMI || !UseMI) in foldAsLoad()
231 LIS.getInstructionIndex(*UseMI))) in foldAsLoad()
241 << " into single use: " << *UseMI); in foldAsLoad()
244 if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second) in foldAsLoad()
247 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS); in foldAsLoad()
251 LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI); in foldAsLoad()
253 if (UseMI->shouldUpdateAdditionalCallInfo()) in foldAsLoad()
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H A DMachineTraceMetrics.cpp697 static bool getDataDeps(const MachineInstr &UseMI, in getDataDeps() argument
701 if (UseMI.isDebugInstr()) in getDataDeps()
705 for (const MachineOperand &MO : UseMI.operands()) { in getDataDeps()
725 static void getPHIDeps(const MachineInstr &UseMI, in getPHIDeps() argument
732 assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI"); in getPHIDeps()
733 for (unsigned i = 1; i != UseMI.getNumOperands(); i += 2) { in getPHIDeps()
734 if (UseMI.getOperand(i + 1).getMBB() == Pred) { in getPHIDeps()
735 Register Reg = UseMI.getOperand(i).getReg(); in getPHIDeps()
744 static void updatePhysDepsDownwards(const MachineInstr *UseMI, in updatePhysDepsDownwards() argument
751 for (const MachineOperand &MO : UseMI->operands()) { in updatePhysDepsDownwards()
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H A DTargetSchedule.cpp172 const MachineInstr *UseMI, unsigned UseOperIdx) const { in computeOperandLatency() argument
182 if (UseMI) { in computeOperandLatency()
184 *UseMI, UseOperIdx); in computeOperandLatency()
206 if (!UseMI) in computeOperandLatency()
210 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
213 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency()
H A DMachineLICM.cpp1090 for (MachineInstr &UseMI : MRI->use_instructions(CopyDstReg)) { in isCopyFeedingInvariantStore()
1091 if (UseMI.mayStore() && isInvariantStore(UseMI, TRI, MRI)) in isCopyFeedingInvariantStore()
1154 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { in HasLoopPHIUse()
1156 if (UseMI.isPHI()) { in HasLoopPHIUse()
1159 if (CurLoop->contains(&UseMI)) in HasLoopPHIUse()
1164 if (isExitBlock(CurLoop, UseMI.getParent())) in HasLoopPHIUse()
1169 if (UseMI.isCopy() && CurLoop->contains(&UseMI)) in HasLoopPHIUse()
1170 Work.push_back(&UseMI); in HasLoopPHIUse()
1185 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) { in HasHighOperandLatency()
1186 if (UseMI.isCopyLike()) in HasHighOperandLatency()
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H A DDetectDeadLanes.cpp339 const MachineInstr &UseMI = *MO.getParent(); in determineInitialUsedLanes() local
340 if (UseMI.isKill()) in determineInitialUsedLanes()
344 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
345 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
346 const MachineOperand &Def = *UseMI.defs().begin(); in determineInitialUsedLanes()
353 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
355 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
357 LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI); in determineInitialUsedLanes()
H A DMachineSSAUpdater.cpp230 MachineInstr *UseMI = U.getParent(); in RewriteUse() local
232 if (UseMI->isPHI()) { in RewriteUse()
233 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U); in RewriteUse()
236 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
246 MachineBasicBlock *UseBB = UseMI->getParent(); in RewriteUse()
H A DOptimizePHIs.cpp170 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) { in IsDeadPHICycle()
171 if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle)) in IsDeadPHICycle()
H A DTailDuplicator.cpp227 MachineInstr *UseMI = UseMO.getParent(); in tailDuplicateAndUpdate() local
232 if (UseMI->isDebugValue()) { in tailDuplicateAndUpdate()
236 if (UseMI->getParent() == DefBB && !UseMI->isPHI()) in tailDuplicateAndUpdate()
241 MachineInstr *UseMI = UseMO->getParent(); in tailDuplicateAndUpdate() local
243 SSAUpdate.GetValueInMiddleOfBlock(UseMI->getParent(), true)); in tailDuplicateAndUpdate()
307 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { in isDefLiveOut()
308 if (UseMI.isDebugValue()) in isDefLiveOut()
310 if (UseMI.getParent() != BB) in isDefLiveOut()
H A DRegisterScavenging.cpp224 MachineBasicBlock::iterator &UseMI) { in spill() argument
269 if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) { in spill()
286 TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI, Register()); in spill()
287 II = std::prev(UseMI); in spill()
303 MachineBasicBlock::iterator UseMI; in scavengeRegisterBackwards() local
H A DRegisterCoalescer.cpp897 MachineInstr *UseMI = MO.getParent(); in removeCopyByCommutingDef() local
898 unsigned OpNo = &MO - &UseMI->getOperand(0); in removeCopyByCommutingDef()
899 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); in removeCopyByCommutingDef()
904 if (UseMI->isRegTiedToDefOperand(OpNo)) in removeCopyByCommutingDef()
942 MachineInstr *UseMI = UseMO.getParent(); in removeCopyByCommutingDef() local
943 if (UseMI->isDebugInstr()) { in removeCopyByCommutingDef()
949 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true); in removeCopyByCommutingDef()
960 if (UseMI == CopyMI) in removeCopyByCommutingDef()
962 if (!UseMI->isCopy()) in removeCopyByCommutingDef()
964 if (UseMI->getOperand(0).getReg() != IntB.reg() || in removeCopyByCommutingDef()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastPreTileConfig.cpp71 void reload(MachineBasicBlock::iterator UseMI, Register VirtReg,
217 void X86FastPreTileConfig::reload(MachineBasicBlock::iterator UseMI, in reload() argument
231 if (UseMI->isCopy()) in reload()
232 TileReg = UseMI->getOperand(0).getReg(); in reload()
241 MachineInstr *NewMI = BuildMI(*UseMI->getParent(), UseMI, DebugLoc(), in reload()
245 BuildMI(*UseMI->getParent(), UseMI, DebugLoc(), TII->get(Opc), TileReg) in reload()
255 if (UseMI->isCopy()) { in reload()
256 UseMI->eraseFromParent(); in reload()
259 for (auto &MO : UseMI->operands()) { in reload()
648 for (MachineInstr &UseMI : MRI->use_instructions(TileReg)) { in configBasicBlock()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp128 MachineInstr &UseMI = *MOUse.getParent(); in localizeInterBlock() local
129 if (MRI->hasOneUse(Reg) && !UseMI.isPHI()) in localizeInterBlock()
130 InsertMBB->insert(UseMI, LocalizedMI); in localizeInterBlock()
165 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) { in localizeIntraBlock()
166 if (!UseMI.isPHI()) in localizeIntraBlock()
167 Users.insert(&UseMI); in localizeIntraBlock()
H A DCombiner.cpp168 MachineInstr *UseMI = MRI.getVRegDef(Use); in appliedCombine() local
169 if (!UseMI) in appliedCombine()
174 if (tryDCE(*UseMI, MRI)) in appliedCombine()
183 WorkList.insert(UseMI); in appliedCombine()
201 for (auto &UseMI : MRI.use_nodbg_instructions(DefReg)) { in addUsersToWorkList() local
202 WorkList.insert(&UseMI); in addUsersToWorkList()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp122 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg() local
123 if (UseMI->getParent() != MBB) in getDefReg()
126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
127 Reg = UseMI->getOperand(0).getReg(); in getDefReg()
130 UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
131 if (UseMI->getParent() != MBB) in getDefReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp677 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
678 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs()
690 LLVM_DEBUG(UseMI.dump()); in recordUnoptimizableWebs()
699 Register SwapDefReg = UseMI.getOperand(0).getReg(); in recordUnoptimizableWebs()
711 LLVM_DEBUG(UseMI.dump()); in recordUnoptimizableWebs()
743 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
744 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs()
785 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
786 int UseIdx = SwapMap[&UseMI]; in markSwapsForRemoval()
790 LLVM_DEBUG(UseMI.dump()); in markSwapsForRemoval()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Subtarget.cpp571 const MachineInstr *UseMI = Use->getInstr(); in adjustSchedDependency() local
572 if (UseMI->getOpcode() == TargetOpcode::BUNDLE) { in adjustSchedDependency()
573 Register Reg = UseMI->getOperand(UseOpIdx).getReg(); in adjustSchedDependency()
574 for (const auto &Op : const_mi_bundle_ops(*UseMI)) { in adjustSchedDependency()
576 UseMI = Op.getParent(); in adjustSchedDependency()
584 SchedModel->computeOperandLatency(DefMI, DefOpIdx, UseMI, UseOpIdx)); in adjustSchedDependency()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.cpp49 MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, in saveScavengerRegister() argument
54 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true); in saveScavengerRegister()

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