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Searched refs:UseIdx (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h185 /// operand index UseIdx. in hasPipelineForwarding() argument
187 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding()
197 if ((FirstUseIdx + UseIdx) >= LastUseIdx) in hasPipelineForwarding()
201 Forwardings[FirstUseIdx + UseIdx];
210 unsigned UseIdx) const { in getOperandLatency()
215 std::optional<unsigned> UseCycle = getOperandCycle(UseClass, UseIdx); in getOperandLatency()
224 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
206 getOperandLatency(unsigned DefClass,unsigned DefIdx,unsigned UseClass,unsigned UseIdx) getOperandLatency() argument
H A DMCSubtargetInfo.h184 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles() argument
191 if (I->UseIdx < UseIdx) in getReadAdvanceCycles()
193 if (I->UseIdx > UseIdx) in getReadAdvanceCycles()
H A DMCSchedule.h101 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
104 unsigned UseIdx;
109 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
107 unsigned UseIdx; global() member
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp680 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs() local
682 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || in recordUnoptimizableWebs()
683 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
691 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
699 if (SwapVector[UseIdx].IsSwap && !SwapVector[UseIdx].IsLoad && in recordUnoptimizableWebs()
700 !SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
712 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
746 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs() local
748 if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) { in recordUnoptimizableWebs()
757 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
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H A DPPCInstrInfo.h341 unsigned UseIdx) const override;
345 unsigned UseIdx) const override { in getOperandLatency() argument
347 UseNode, UseIdx); in getOperandLatency()
H A DPPCInstrInfo.cpp170 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { in getOperandLatency()
172 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency()
2070 unsigned UseIdx; in onlyFoldImmediate() local
2071 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx) in onlyFoldImmediate()
2072 if (UseMI.getOperand(UseIdx).isReg() && in onlyFoldImmediate()
2073 UseMI.getOperand(UseIdx).getReg() == Reg) in onlyFoldImmediate()
2076 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"); in onlyFoldImmediate()
2077 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); in onlyFoldImmediate()
2079 const MCOperandInfo *UseInfo = &UseMCID.operands()[UseIdx]; in onlyFoldImmediate()
2109 UseMI.getOperand(UseIdx).setReg(ZeroReg); in onlyFoldImmediate()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp108 SlotIndex UseIdx) const { in allUsesAvailableAt()
110 UseIdx = std::max(UseIdx, UseIdx.getRegSlot(true)); in allUsesAvailableAt()
131 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) in allUsesAvailableAt()
134 if (OVNI != li.getVNInfoAt(UseIdx)) in allUsesAvailableAt()
146 if (!SR.liveAt(UseIdx)) in allUsesAvailableAt()
159 SlotIndex UseIdx, bool cheapAsAMove) { in canRematerializeAt() argument
176 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
H A DLiveIntervalCalc.cpp171 SlotIndex UseIdx; in extendToUses()
176 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo + 1).getMBB()); in extendToUses()
188 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber); in extendToUses()
193 extend(LR, UseIdx, Reg, Undefs); in extendToUses()
172 SlotIndex UseIdx; extendToUses() local
H A DTargetSchedule.cpp162 unsigned UseIdx = 0; in findUseIdx()
166 ++UseIdx;
168 return UseIdx; in computeOperandLatency()
216 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency() local
217 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
158 unsigned UseIdx = 0; findUseIdx() local
H A DInlineSpiller.cpp631 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); in reMaterializeFor() local
632 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
639 LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI); in reMaterializeFor()
647 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx); in reMaterializeFor()
651 if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) { in reMaterializeFor()
653 LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI); in reMaterializeFor()
661 LLVM_DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI); in reMaterializeFor()
678 LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI); in reMaterializeFor()
706 LLVM_DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n'); in reMaterializeFor()
H A DRegisterCoalescer.cpp318 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
886 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); in removeCopyByCommutingDef() local
887 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
936 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true); in removeCopyByCommutingDef() local
937 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
957 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef()
1228 SlotIndex UseIdx = LIS->getInstructionIndex(MI); in removePartialRedundancy() local
1229 if (!IntB.liveAt(UseIdx)) in removePartialRedundancy()
1756 SlotIndex UseIdx = LIS->getInstructionIndex(MI); in eliminateUndefCopy() local
1764 if (SR.liveAt(UseIdx)) { in eliminateUndefCopy()
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H A DMachineCopyPropagation.cpp423 const MachineInstr &UseI, unsigned UseIdx);
426 unsigned UseIdx);
556 const MachineInstr &Copy, const MachineInstr &UseI, unsigned UseIdx) { in isBackwardPropagatableRegClassCopy() argument
562 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isBackwardPropagatableRegClassCopy()
575 unsigned UseIdx) { in isForwardableRegClassCopy() argument
583 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isForwardableRegClassCopy()
H A DMachineVerifier.cpp280 SlotIndex UseIdx, const LiveRange &LR,
2713 unsigned MONum, SlotIndex UseIdx, in checkLivenessAtUse() argument
2718 LiveQueryResult LRQ = LR.Query(UseIdx); in checkLivenessAtUse()
2726 report_context(UseIdx); in checkLivenessAtUse()
2734 report_context(UseIdx); in checkLivenessAtUse()
2828 SlotIndex UseIdx; in checkLiveness() local
2831 UseIdx = LiveInts->getMBBEndIdx( in checkLiveness()
2834 UseIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness()
2842 checkLivenessAtUse(MO, MONum, UseIdx, *LR, Unit); in checkLiveness()
2848 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg); in checkLiveness()
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H A DMachineCombiner.cpp234 int UseIdx = in getDepth() local
237 InstrPtr, UseIdx); in getDepth()
H A DSplitKit.h382 /// defFromParent - Define Reg from ParentVNI at UseIdx using either
385 SlotIndex UseIdx, MachineBasicBlock &MBB,
H A DTargetInstrInfo.cpp1444 SDNode *UseNode, unsigned UseIdx) const { in getOperandLatency()
1455 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1645 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { in getOperandLatency()
1648 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DAbstractCallSite.cpp100 unsigned UseIdx = CB->getArgOperandNo(U); in AbstractCallSite() local
107 if (CBCalleeIdx != UseIdx) in AbstractCallSite()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h199 SlotIndex UseIdx) const;
204 bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx,
H A DTargetInstrInfo.h1771 unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const;
1784 const MachineInstr &UseMI, unsigned UseIdx) const;
1814 unsigned UseIdx) const { in hasHighOperandLatency() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h328 unsigned UseIdx) const override;
332 unsigned UseIdx) const override;
441 unsigned UseClass, unsigned UseIdx,
445 unsigned UseClass, unsigned UseIdx,
451 unsigned UseIdx,
458 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;
473 unsigned UseIdx) const override;
H A DARMBaseInstrInfo.cpp3953 unsigned UseIdx, unsigned UseAlign) const { in getVSTMUseCycle() argument
3954 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
3956 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3992 unsigned UseIdx, unsigned UseAlign) const { in getSTMUseCycle() argument
3993 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
3995 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
4020 unsigned UseIdx, unsigned UseAlign) const { in getOperandLatency() argument
4024 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
4025 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
4075 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp470 int UseIdx = -1; in adjustSchedDependency() local
474 UseIdx = OpNum; in adjustSchedDependency()
479 if (UseIdx == -1) in adjustSchedDependency()
483 InstrInfo.getOperandLatency(&InstrItins, *SrcInst, 0, *DDst, UseIdx); in adjustSchedDependency()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp702 unsigned UseIdx; in foldImmediate() local
707 UseIdx = 2; in foldImmediate()
730 UseIdx = 1; in foldImmediate()
738 UseIdx = 2; in foldImmediate()
747 UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg()); in foldImmediate()
749 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); in foldImmediate()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1266 for (unsigned UseIdx = 0, EndIdx = Reads.size(); UseIdx != EndIdx; in GenSchedClassTables() local
1267 ++UseIdx) { in GenSchedClassTables()
1269 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1293 RAEntry.UseIdx = UseIdx; in GenSchedClassTables()
1399 OS << " {" << RAEntry.UseIdx << ", " in EmitSchedClassTables()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp707 unsigned UseIdx; in foldImmediate() local
719 UseIdx = 2; in foldImmediate()
721 UseIdx = 2, CommuteIdx = 1; in foldImmediate()
733 UseIdx = 2; in foldImmediate()
735 UseIdx = 2, CommuteIdx = 1; in foldImmediate()
744 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx)) in foldImmediate()
751 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); in foldImmediate()

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