| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrItineraries.h | 185 /// operand index UseIdx. in hasPipelineForwarding() argument
187 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding()
197 if ((FirstUseIdx + UseIdx) >= LastUseIdx) in hasPipelineForwarding()
201 Forwardings[FirstUseIdx + UseIdx];
210 unsigned UseIdx) const { in getOperandLatency()
215 std::optional<unsigned> UseCycle = getOperandCycle(UseClass, UseIdx); in getOperandLatency()
224 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
206 getOperandLatency(unsigned DefClass,unsigned DefIdx,unsigned UseClass,unsigned UseIdx) getOperandLatency() argument
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| H A D | MCSubtargetInfo.h | 187 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles() argument
194 if (I->UseIdx < UseIdx) in getReadAdvanceCycles()
196 if (I->UseIdx > UseIdx) in getReadAdvanceCycles()
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| H A D | MCSchedule.h | 109 unsigned UseIdx; member
114 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXSwapRemoval.cpp | 678 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs() local
680 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || in recordUnoptimizableWebs()
681 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
689 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
697 if (SwapVector[UseIdx].IsSwap && !SwapVector[UseIdx].IsLoad && in recordUnoptimizableWebs()
698 !SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
710 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
744 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs() local
746 if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) { in recordUnoptimizableWebs()
755 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
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| H A D | PPCInstrInfo.h | 451 unsigned UseIdx) const override;
455 unsigned UseIdx) const override { in getOperandLatency() argument
457 UseNode, UseIdx); in getOperandLatency()
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| H A D | PPCInstrInfo.cpp | 168 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { in getOperandLatency()
170 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency()
2093 unsigned UseIdx; in onlyFoldImmediate() local
2094 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx) in onlyFoldImmediate()
2095 if (UseMI.getOperand(UseIdx).isReg() && in onlyFoldImmediate()
2096 UseMI.getOperand(UseIdx).getReg() == Reg) in onlyFoldImmediate()
2099 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"); in onlyFoldImmediate()
2100 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); in onlyFoldImmediate()
2102 const MCOperandInfo *UseInfo = &UseMCID.operands()[UseIdx]; in onlyFoldImmediate()
2132 UseMI.getOperand(UseIdx).setReg(ZeroReg); in onlyFoldImmediate()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRangeEdit.cpp | 108 SlotIndex UseIdx) const { in allUsesAvailableAt()
110 UseIdx = std::max(UseIdx, UseIdx.getRegSlot(true)); in allUsesAvailableAt()
131 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) in allUsesAvailableAt()
134 if (OVNI != li.getVNInfoAt(UseIdx)) in allUsesAvailableAt()
146 if (!SR.liveAt(UseIdx)) in allUsesAvailableAt()
159 SlotIndex UseIdx) { in canRematerializeAt() argument
172 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
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| H A D | LiveIntervalCalc.cpp | 170 SlotIndex UseIdx; in extendToUses() local
175 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo + 1).getMBB()); in extendToUses()
187 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber); in extendToUses()
192 extend(LR, UseIdx, Reg, Undefs); in extendToUses()
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| H A D | TargetSchedule.cpp | 159 unsigned UseIdx = 0; in findUseIdx() local
163 ++UseIdx; in findUseIdx()
165 return UseIdx; in findUseIdx()
213 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency() local
214 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
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| H A D | InlineSpiller.cpp | 628 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); in hasPhysRegAvailable() local
629 SlotIndex PrevIdx = UseIdx.getPrevSlot(); in hasPhysRegAvailable()
632 if (!Matrix->checkInterference(PrevIdx, UseIdx, PhysReg)) in hasPhysRegAvailable()
648 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); in reMaterializeFor() local
649 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
656 LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI); in reMaterializeFor()
664 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx); in reMaterializeFor()
668 if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx)) { in reMaterializeFor()
670 LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI); in reMaterializeFor()
678 LLVM_DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI); in reMaterializeFor()
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| H A D | RegisterCoalescer.cpp | 318 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
899 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); in removeCopyByCommutingDef() local
900 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
949 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true); in removeCopyByCommutingDef() local
950 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
970 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef()
1241 SlotIndex UseIdx = LIS->getInstructionIndex(MI); in removePartialRedundancy() local
1242 if (!IntB.liveAt(UseIdx)) in removePartialRedundancy()
1813 SlotIndex UseIdx = LIS->getInstructionIndex(MI); in eliminateUndefCopy() local
1821 if (SR.liveAt(UseIdx)) { in eliminateUndefCopy()
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| H A D | SplitKit.h | 386 SlotIndex UseIdx) const;
391 SlotIndex UseIdx, MachineBasicBlock &MBB,
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| H A D | MachineCopyPropagation.cpp | 479 const MachineInstr &UseI, unsigned UseIdx);
482 unsigned UseIdx);
638 const MachineInstr &Copy, const MachineInstr &UseI, unsigned UseIdx) { in isBackwardPropagatableRegClassCopy() argument
644 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isBackwardPropagatableRegClassCopy()
657 unsigned UseIdx) { in isForwardableRegClassCopy() argument
665 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isForwardableRegClassCopy()
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| H A D | SplitKit.cpp | 593 SlotIndex UseIdx) const { in rematWillIncreaseRestriction()
594 const MachineInstr *UseMI = LIS.getInstructionFromIndex(UseIdx); in rematWillIncreaseRestriction()
623 SlotIndex UseIdx, MachineBasicBlock &MBB, in defFromParent() argument
634 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx); in defFromParent()
641 Edit->canRematerializeAt(RM, OrigVNI, UseIdx)) { in defFromParent()
642 if (!rematWillIncreaseRestriction(RM.OrigMI, MBB, UseIdx)) { in defFromParent()
650 << UseIdx in defFromParent()
659 if (S.liveAt(UseIdx)) in defFromParent()
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| H A D | MachineVerifier.cpp | 331 SlotIndex UseIdx, const LiveRange &LR,
2842 unsigned MONum, SlotIndex UseIdx, in checkLivenessAtUse() argument
2852 report_context(UseIdx); in checkLivenessAtUse()
2856 LiveQueryResult LRQ = LR.Query(UseIdx); in checkLivenessAtUse()
2864 report_context(UseIdx); in checkLivenessAtUse()
2872 report_context(UseIdx); in checkLivenessAtUse()
2975 SlotIndex UseIdx; in checkLiveness() local
2978 UseIdx = LiveInts->getMBBEndIdx( in checkLiveness()
2981 UseIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness()
2989 checkLivenessAtUse(MO, MONum, UseIdx, *LR, VirtRegOrUnit(Unit)); in checkLiveness()
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| H A D | MachineCombiner.cpp | 231 int UseIdx = in getDepth() local
234 InstrPtr, UseIdx); in getDepth()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AbstractCallSite.cpp | 100 unsigned UseIdx = CB->getArgOperandNo(U); in AbstractCallSite() local
107 if (CBCalleeIdx != UseIdx) in AbstractCallSite()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | LiveRangeEdit.h | 199 SlotIndex UseIdx) const;
203 bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx);
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| H A D | TargetInstrInfo.h | 1846 unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const;
1859 const MachineInstr &UseMI, unsigned UseIdx) const;
1889 unsigned UseIdx) const { in hasHighOperandLatency() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 325 unsigned UseIdx) const override;
329 unsigned UseIdx) const override;
432 unsigned UseClass, unsigned UseIdx,
436 unsigned UseClass, unsigned UseIdx,
442 unsigned UseIdx,
449 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;
464 unsigned UseIdx) const override;
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| H A D | ARMBaseInstrInfo.cpp | 3796 unsigned UseIdx, unsigned UseAlign) const { in getVSTMUseCycle() argument
3797 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
3799 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3835 unsigned UseIdx, unsigned UseAlign) const { in getSTMUseCycle() argument
3836 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
3838 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
3863 unsigned UseIdx, unsigned UseAlign) const { in getOperandLatency() argument
3867 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3868 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3918 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 471 int UseIdx = -1; in adjustSchedDependency() local
475 UseIdx = OpNum; in adjustSchedDependency()
480 if (UseIdx == -1) in adjustSchedDependency()
484 InstrInfo.getOperandLatency(&InstrItins, *SrcInst, 0, *DDst, UseIdx); in adjustSchedDependency()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.cpp | 700 unsigned UseIdx; in foldImmediate() local
705 UseIdx = 2; in foldImmediate()
728 UseIdx = 1; in foldImmediate()
736 UseIdx = 2; in foldImmediate()
745 UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg()); in foldImmediate()
747 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); in foldImmediate()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 1238 for (unsigned UseIdx = 0, EndIdx = Reads.size(); UseIdx != EndIdx; in genSchedClassTables() local
1239 ++UseIdx) { in genSchedClassTables()
1241 findReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in genSchedClassTables()
1270 RAEntry.UseIdx = UseIdx; in genSchedClassTables()
1376 OS << " {" << RAEntry.UseIdx << ", " in emitSchedClassTables()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 729 unsigned UseIdx; in foldImmediate() local
741 UseIdx = 2; in foldImmediate()
743 UseIdx = 2, CommuteIdx = 1; in foldImmediate()
755 UseIdx = 2; in foldImmediate()
757 UseIdx = 2, CommuteIdx = 1; in foldImmediate()
766 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx)) in foldImmediate()
773 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); in foldImmediate()
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