| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Interpreter.cpp | 57 memset(&ExitValue.Untyped, 0, sizeof(ExitValue.Untyped)); in Interpreter()
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| H A D | Execution.cpp | 865 memset(&ExitValue.Untyped, 0, sizeof(ExitValue.Untyped)); in popStackAndReturnValueToCaller()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/ |
| H A D | GenericValue.h | 33 unsigned char Untyped[8]; member
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ValueTypes.cpp | 182 case MVT::Untyped: return "Untyped"; in getEVTString()
279 return MVT::Untyped; in getEVT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTX.h | 122 Untyped enumerator
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| H A D | NVPTXISelDAGToDAG.cpp | 896 return NVPTX::PTXLdStInstCode::Untyped; in getLdStRegType()
1118 FromType = NVPTX::PTXLdStInstCode::Untyped; in tryLoadVector()
1905 ToType = NVPTX::PTXLdStInstCode::Untyped; in tryStoreVector()
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| /freebsd/contrib/llvm-project/clang/include/clang/Analysis/Analyses/ |
| H A D | UnsafeBufferUsageGadgets.def | 48 FIXABLE_GADGET(UUCAddAssign) // 'Ptr += n' in an Unspecified Untyped Context
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXInstPrinter.cpp | 260 else if (Imm == NVPTX::PTXLdStInstCode::Untyped) in printLdStCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1462 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops); in createTuple()
1687 const EVT ResTys[] = {MVT::Untyped, MVT::Other}; in SelectLoad()
1718 MVT::Untyped, MVT::Other}; in SelectPostLoad()
1835 SDNode *WhilePair = CurDAG->getMachineNode(Opc, DL, MVT::Untyped, Ops); in SelectPExtPair()
1851 SDNode *WhilePair = CurDAG->getMachineNode(Opc, DL, MVT::Untyped, Ops); in SelectWhilePair()
1867 SDNode *Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, Ops); in SelectCVTIntrinsic()
1903 Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, in SelectDestructiveMultiIntrinsic()
1906 Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, Zdn, Zm); in SelectDestructiveMultiIntrinsic()
1934 const EVT ResTys[] = {MVT::Untyped, MVT::Other}; in SelectPredicatedLoad()
1969 const EVT ResTys[] = {MVT::Untyped, MVT::Other}; in SelectContiguousMultiVectorLoad()
[all …]
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| H A D | AArch64ISelLowering.cpp | 25959 DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0); in createGPRPairNode()
26000 Opcode, SDLoc(N), DAG.getVTList(MVT::Untyped, MVT::Other), Ops); in ReplaceCMP_SWAP_128Results()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2910 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, AccLo, AccHi), 0)); in SelectCDE_CXxD()
2931 SDNode *InstrNode = CurDAG->getMachineNode(Opcode, Loc, MVT::Untyped, Ops); in SelectCDE_CXxD()
4064 {MVT::Untyped, MVT::Other}, Ops); in Select()
4092 createGPRPairNode(MVT::Untyped, N->getOperand(1), N->getOperand(2)); in Select()
4769 ResTys.push_back(MVT::Untyped); in Select()
4832 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0)); in Select()
5792 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped); in tryInlineAsm()
5796 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped, in tryInlineAsm()
5822 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0); in tryInlineAsm()
5827 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped); in tryInlineAsm()
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| H A D | ARMISelLowering.cpp | 10482 DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0); in createGPRPairNode()
10496 DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other), Ops); in ReplaceCMP_SWAP_64Results()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 325 if (VT == MVT::Untyped) in isTypeLegalForClass()
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| H A D | ValueTypes.td | 280 let LLVMName = "Untyped";
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| H A D | SelectionDAGNodes.h | 2269 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 445 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped) in getNumRegisters()
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| H A D | SystemZISelLowering.cpp | 1555 MVT::Untyped, Hi, Lo); in lowerI128ToGR128()
1581 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
1593 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in joinRegisterPartsIntoValue()
3179 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped, Op0, Op1); in lowerGR128Binary()
6301 SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::Other); in LowerOperationWrapper()
6337 SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other); in LowerOperationWrapper()
7971 if (Op.getResNo() != 0 || VT == MVT::Untyped) in computeKnownBitsForTargetNode()
9660 if (VT == MVT::Untyped) in getRepRegClassFor()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 307 if (VT == MVT::Untyped) in getRepRegClassFor()
1268 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, in lowerMulDiv()
1287 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); in initAccumulator()
1341 ResTys.push_back((Ty == MVT::i64) ? MVT::Untyped : Ty); in lowerDSPIntr()
1345 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val; in lowerDSPIntr()
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| H A D | MipsISelLowering.cpp | 1051 CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, BottomHalf, TopHalf); in performMADD_MSUBCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 289 CurDAG.getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops); in createTuple()
363 CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); in selectVLSEG()
403 MachineSDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, in selectVLSEGFF()
456 CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); in selectVLXSEG()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 320 if (VT == MVT::Untyped) { in GetCostForDef()
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| H A D | SelectionDAGBuilder.cpp | 6314 setValue(&I, DAG.getNode(ISD::CONVERGENCECTRL_ANCHOR, sdl, MVT::Untyped)); in visitConvergenceControl()
6317 setValue(&I, DAG.getNode(ISD::CONVERGENCECTRL_ENTRY, sdl, MVT::Untyped)); in visitConvergenceControl()
6322 setValue(&I, DAG.getNode(ISD::CONVERGENCECTRL_LOOP, sdl, MVT::Untyped, in visitConvergenceControl()
9628 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { in getRegistersForValue()
10039 : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT) in visitInlineAsm()
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| H A D | SelectionDAG.cpp | 2284 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), std::nullopt); in getRegisterMask()
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| H A D | DAGCombiner.cpp | 6497 if (PtrType == MVT::Untyped || PtrType.isExtended()) in isLegalNarrowLdSt()
19358 if (PtrType == MVT::Untyped || PtrType.isExtended()) in isLegal()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenDAGPatterns.cpp | 2714 if (!VVT.isSimple() || VVT.getSimple() != MVT::Untyped) in ApplyTypeConstraints()
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