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Searched refs:Untyped (Results 1 – 25 of 29) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DInterpreter.cpp57 memset(&ExitValue.Untyped, 0, sizeof(ExitValue.Untyped)); in Interpreter()
H A DExecution.cpp865 memset(&ExitValue.Untyped, 0, sizeof(ExitValue.Untyped)); in popStackAndReturnValueToCaller()
/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/
H A DGenericValue.h33 unsigned char Untyped[8]; member
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp189 case MVT::Untyped: return "Untyped"; in getEVTString()
304 return MVT::Untyped; in getEVT()
/freebsd/contrib/llvm-project/clang/include/clang/Analysis/Analyses/
H A DUnsafeBufferUsageGadgets.def49 FIXABLE_GADGET(UUCAddAssign) // 'Ptr += n' in an Unspecified Untyped Context
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTX.h194 enum FromType { Unsigned = 0, Signed, Float, Untyped }; enumerator
H A DNVPTXISelDAGToDAG.cpp1042 : NVPTX::PTXLdStInstCode::Untyped; in tryLoad()
1122 : NVPTX::PTXLdStInstCode::Untyped; in tryLoadVector()
1192 : NVPTX::PTXLdStInstCode::Untyped; in tryLDG()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1466 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops); in createTuple()
1738 const EVT ResTys[] = {MVT::Untyped, MVT::Other}; in SelectLoad()
1769 MVT::Untyped, MVT::Other}; in SelectPostLoad()
1886 SDNode *WhilePair = CurDAG->getMachineNode(Opc, DL, MVT::Untyped, Ops); in SelectPExtPair()
1902 SDNode *WhilePair = CurDAG->getMachineNode(Opc, DL, MVT::Untyped, Ops); in SelectWhilePair()
1918 SDNode *Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, Ops); in SelectCVTIntrinsic()
1935 CurDAG->getMachineNode(Opcode, DL, {MVT::Untyped, MVT::Other}, Ops); in SelectCVTIntrinsicFP8()
1974 Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, in SelectDestructiveMultiIntrinsic()
1977 Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, Zdn, Zm); in SelectDestructiveMultiIntrinsic()
2005 const EVT ResTys[] = {MVT::Untyped, MVT::Other}; in SelectPredicatedLoad()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXInstPrinter.cpp347 case NVPTX::PTXLdStInstCode::Untyped: in printLdStCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2901 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, AccLo, AccHi), 0)); in SelectCDE_CXxD()
2922 SDNode *InstrNode = CurDAG->getMachineNode(Opcode, Loc, MVT::Untyped, Ops); in SelectCDE_CXxD()
4058 {MVT::Untyped, MVT::Other}, Ops); in Select()
4086 createGPRPairNode(MVT::Untyped, N->getOperand(1), N->getOperand(2)); in Select()
4753 ResTys.push_back(MVT::Untyped); in Select()
4816 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0)); in Select()
5776 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped); in tryInlineAsm()
5780 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped, in tryInlineAsm()
5806 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0); in tryInlineAsm()
5811 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped); in tryInlineAsm()
H A DARMISelLowering.cpp10528 DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0); in createGPRPairNode2xi32()
10554 DAG.getVTList(MVT::Untyped, MVT::Untyped, MVT::Other), Ops); in ReplaceCMP_SWAP_64Results()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp301 CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); in selectVLSEG()
330 MachineSDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, in selectVLSEGFF()
380 CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); in selectVLXSEG()
1805 RISCV::LD_RV32, DL, {MVT::Untyped, MVT::Other}, Ops); in Select()
1829 RegPair = CurDAG->getRegister(RISCV::X0_Pair, MVT::Untyped); in Select()
1837 MVT::Untyped, Ops), in Select()
H A DRISCVISelLowering.cpp2402 *RegisterVT == MVT::Untyped) in getNumRegisters()
23929 NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
24018 NumParts == 1 && PartVT == MVT::Untyped) { in joinRegisterPartsIntoValue()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h324 if (VT == MVT::Untyped) in isTypeLegalForClass()
H A DValueTypes.td329 let LLVMName = "Untyped";
H A DSelectionDAGNodes.h2384 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h459 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped) in getNumRegisters()
H A DSystemZISelLowering.cpp1883 MVT::Untyped, Hi, Lo); in lowerI128ToGR128()
1909 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
1921 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in joinRegisterPartsIntoValue()
3572 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped, Op0, Op1); in lowerGR128Binary()
7228 SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::Other); in LowerOperationWrapper()
7264 SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other); in LowerOperationWrapper()
9295 if (Op.getResNo() != 0 || VT == MVT::Untyped) in computeKnownBitsForTargetNode()
10988 if (VT == MVT::Untyped) in getRepRegClassFor()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp346 if (VT == MVT::Untyped) in getRepRegClassFor()
1312 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, in lowerMulDiv()
1331 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); in initAccumulator()
1385 ResTys.push_back((Ty == MVT::i64) ? MVT::Untyped : Ty); in lowerDSPIntr()
1389 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val; in lowerDSPIntr()
H A DMipsISelLowering.cpp1103 CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, BottomHalf, TopHalf); in performMADD_MSUBCombine()
1112 SDValue MAdd = CurDAG.getNode(Opcode, DL, MVT::Untyped, MAddOps); in performMADD_MSUBCombine()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaExprCXX.cpp2668 enum class ResolveMode { Typed, Untyped }; enumerator
2841 enum class DeallocLookupMode { Untyped, OptionallyTyped }; enumerator
2850 bool RemoveTypedDecl = Mode == DeallocLookupMode::Untyped; in LookupGlobalDeallocationFunctions()
2900 S, R, Range, ResolveMode::Untyped, Args, IAP.PassAlignment, Operator, in resolveAllocationOverload()
3108 : DeallocLookupMode::Untyped; in FindAllocationFunctions()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp320 if (VT == MVT::Untyped) { in GetCostForDef()
H A DSelectionDAGBuilder.cpp6397 setValue(&I, DAG.getNode(ISD::CONVERGENCECTRL_ANCHOR, sdl, MVT::Untyped)); in visitConvergenceControl()
6400 setValue(&I, DAG.getNode(ISD::CONVERGENCECTRL_ENTRY, sdl, MVT::Untyped)); in visitConvergenceControl()
6405 setValue(&I, DAG.getNode(ISD::CONVERGENCECTRL_LOOP, sdl, MVT::Untyped, in visitConvergenceControl()
9791 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { in getRegistersForValue()
10201 : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT) in visitInlineAsm()
H A DSelectionDAG.cpp2342 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), {}); in getRegisterMask()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenDAGPatterns.cpp2787 if (!VVT.isSimple() || VVT.getSimple() != MVT::Untyped) in ApplyTypeConstraints()

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